ICS1893BF Data Sheet Rev. E - Release
Table of Contents
Table of Contents
Section
Title
Page
7.14
Register 19: Extended Control Register 2 .............................................................87
Node Configuration (bit 19.15) ...............................................................................88
Hardware/Software Priority Status (bit 19.14) ........................................................88
Remote Fault (bit 19.13) ........................................................................................88
ICS Reserved (bits 19.12:10) .................................................................................88
Auto-MDI/MDIX (bits 19. 9:13)................................................................................88
Twisted Pair Tri-State Enable, TPTRI (bit 19.7) .....................................................89
ICS Reserved (bits 19.6:1) .....................................................................................89
Automatic 100Base-TX Power-Down (bit 19.0) .....................................................89
7.14.1
7.14.2
7.14.3
7.14.4
7.14.5
7.14.6
7.14.7
7.14.8
Chapter 8
8.1
Pin Diagram, Listings, and Descriptions.......................................................................90
ICS1893BF Pin Diagram ........................................................................................90
8.2
ICS1893BF Pin Descriptions .................................................................................91
Transformer Interface Pins .....................................................................................92
Multi-Function (Multiplexed) Pins: PHY Address and LED Pins .............................92
Configuration Pins...................................................................................................96
MAC Interface Pins.................................................................................................97
Ground and Power Pins........................................................................................101
ICS1893BK Pin Diagram with MDIX Pinout (56L, 8x8 MLF2) ..............................102
ICS1893BK Pin Descriptions ................................................................................103
Transformer Interface Pins ...................................................................................104
Ground and Power Pins........................................................................................105
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.3
8.3.1
8.3.2
8.3.3
Chapter 9
9.1
DC and AC Operating Conditions.................................................................................106
Absolute Maximum Ratings .................................................................................106
9.2
9.3
9.4
9.4.1
9.4.2
9.4.3
9.4.4
9.5
9.5.1
9.5.2
9.5.3
9.5.4
9.5.5
9.5.6
9.5.7
9.5.8
9.5.9
9.5.10
9.5.11
9.5.12
9.5.13
Recommended Operating Conditions ..................................................................106
Recommended Component Values .....................................................................107
DC Operating Characteristics ..............................................................................108
DC Operating Characteristics for Supply Current ................................................108
DC Operating Characteristics for TTL Inputs and Outputs ..................................108
DC Operating Characteristics for REF_IN ...........................................................109
DC Operating Characteristics for Media Independent Interface ..........................109
Timing Diagrams ..................................................................................................110
Timing for Clock Reference In (REF_IN) Pin .......................................................110
Timing for Transmit Clock (TXCLK) Pins .............................................................111
Timing for Receive Clock (RXCLK) Pins ..............................................................112
100M MII: Synchronous Transmit Timing .............................................................113
10M MII: Synchronous Transmit Timing ..............................................................114
100M/MII Media Independent Interface: Synchronous Receive Timing ...............115
MII Management Interface Timing .......................................................................116
10M Media Independent Interface: Receive Latency ...........................................117
10M Media Independent Interface: Transmit Latency...........................................118
100M/MII Media Independent Interface: Transmit Latency...................................119
100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)................120
10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)..................121
100M MII Media Independent Interface: Receive Latency....................................122
ICS1893BF, Rev. E, 8/11/09
August, 2009
Copyright © 2009, IDT, Inc.
All rights reserved.
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