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181M-01 PDF预览

181M-01

更新时间: 2024-10-01 19:54:19
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
8页 150K
描述
Clock Generator, 75MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8

181M-01 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.150 INCH, SOIC-8
针数:8Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.61Is Samacsys:N
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.9 mm湿度敏感等级:1
端子数量:8最高工作温度:70 °C
最低工作温度:最大输出时钟频率:75 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE电源:3.3/5 V
主时钟/晶体标称频率:40 MHz认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Clock Generators
最大压摆率:50 mA最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:3.9 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

181M-01 数据手册

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DATASHEET  
LOW EMI CLOCK GENERATOR  
ICS181-01  
Description  
Features  
The ICS181-01 generates a low EMI output clock from  
a clock or crystal input. The device uses IDT’s  
proprietary mix of analog and digital Phase-Locked  
Loop (PLL) technology to spread the frequency  
spectrum of the output, thereby reducing the frequency  
amplitude peaks by several dB.  
Pin and function compatible to Cypress W181-01  
Packaged in 8-pin SOIC  
Provides a spread spectrum output clock  
Accepts a clock input and provides same frequency  
dithered output  
Input frequency of 28 to 75 MHz for Clock input  
The ICS181-01 offers down spread selection of -1.25%  
and -3.75%. Refer to the MK1714-01/02 for the widest  
selection of input frequencies and multipliers.  
Peak reduction by 7dB - 14dB typical on 3rd - 19th  
odd harmonics  
IDT offers a complete line of EMI reducing clock  
generators. Consult us when you need to remove  
crystals and oscillators from your board.  
Spread percentage selection for -1.25% and -3.75%  
Operating voltage of 3.3 V and 5 V  
Available in Pb (lead) free package  
Industrial temperature range available  
Advanced, low-power CMOS process  
NOTE: EOL for non-green parts to occur on  
5/13/10 per PDN U-09-01  
Block Diagram  
VDD  
FS2:1  
SS%  
PLL Clock  
Synthesis  
and Spread  
Spectrum  
Circuitry  
CLK  
X1/CLKIN  
Clock Buffer/  
Crystal  
Oscillator  
X2  
GND  
IDT™ / ICS™ LOW EMI CLOCK GENERATOR  
1
ICS181-01  
REV C 081009  

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