LOW INDUCTANCE CHIP CAPACITORS
These MLC capacitors are specially designed to lower
inductance by altering the aspect ratio of the termination
in conjunction with improved conductivity of the electrodes.
This inherent low ESL and ESR design improves the
capacitor circuit performance by lowering the current
change noise pulse and voltage drop. The system will
benefit by lower power consumption, increased efficiency,
and higher operating speeds.
FEATURES
• Low ESL
• Low ESR
• High Resonant Frequency
• Small Size
APPLICATIONS
• High Speed Microprocessors
• AC Noise Reduction in multi-chip modules (MCM)
• High speed digital equipment
CAPACITANCE
SELECTION
50 V
25 V
16 V
50 V
25 V
16 V
B15 / 0508
Inches
(mm)
.050 .010
.080 .010
.050 Max.
.010 .005
(1.27 .25)
(2.03 .25)
(1.27)
L
W
T
DIELECTRIC
X7R
NPO
Z5U
(0.25 .13)
E/B
B18 / 0612
Inches
(mm)
.062 .010
.125 .010
.060 Max.
.010 .005
(1.57 .25)
(3.17 .25)
(1.52)
L
W
T
(0.25 .13)
E/B
Dielectric specifications are listed on page 28 & 29.
HOW TO
ORDER
LOW
INDUCTANCE
500
B18
W
473
K
V
4
E
CASE SIZE
B15 = 0508
B18 = 0612
TERMINATION
V = Nickel Barrier
VOLTAGE
DIELECTRIC
CAPACITANCE
TOLERANCE
TAPE MODIFIER
160 = 16 V
250 = 25 V
500 = 50 V
N = NPO
W = X7R
Z = Z5U
1st two digits are
significant; third digit
denotes number of
zeros.
J
=
=
=
5%
10%
20%
Code
Type Reel
Plastic 7"
Plastic 13"
K
E
U
T
M
Z
= +80% -20%
Paper
7"
MARKING
4 = Unmarked
R
Paper 13"
474 = 0.47 µF
105 = 1.00 µF
Tape specs. per EIA RS481
P/N written: 500B18W473KV4E
24
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