Core1553BBC MIL-STD-1553B Bus Controller
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Synthesis Scripts
Product Summary
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Actel-Developed Testbenches, VHDL and Verilog
Intended Use
Synthesis and Simulation Support
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1553B Bus Controller (BC)
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Synthesis: Synplicity®, Synopsys® (Design Compiler®/
FPGA CompilerTM/FPGA ExpressTM), ExemplarTM
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DMA Backend Interface to External Memory
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Simulation: Vital-Compliant VHDL Simulators and
OVI-Compliant Verilog Simulators
Key Features
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Supports MIL-STD-1553B
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Interfaces to External RAM
Verification and Compliance
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Supports up to 128kbytes of Memory
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Actel-Developed Simulation Testbench
Synchronous
Interface
or
Asynchronous
Backend
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Core Implemented on the 1553B BC Development
System
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Backend Interface Identical to Core1553BRT
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Third-Party 1553B Compliance Testing of the
1553B Encoder and Decoder Blocks Implemented
in an A54SXA32-STD Device
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Selectable Clock Rate of 12, 16, 20, or 24 MHz
Provides Direct CPU Access to Memory
Interfaces to Standard 1553B Transceivers
Fully Automated Message Scheduling
Development System (Optional)
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Frame Support
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Complete 1553B BC Implementation in an SX-A
Device
Conditional Branching and Sub-routines
Variable Inter-message Gaps and RT Response
Times
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Includes a PCI Interface for Host CPU Connection
Includes Transceivers and Bus Termination
Components
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Real Time Clock for Message Scheduling
Asynchronous Message Support
Contents
Supported Families
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Fusion
General Description ................................................... 2
Core1553BBC Device Requirements .......................... 4
Core1553BBC Verification and Compliance .............. 4
MIL-STD-1553B Bus Overview .................................... 4
I/O Signal Descriptions ............................................. 6
Bus Transceivers ........................................................ 20
Development System ............................................... 20
Typical BC System ..................................................... 22
Specifications ............................................................ 24
Ordering Information .............................................. 28
List of Changes ......................................................... 29
Datasheet Categories ............................................... 29
ProASIC3/E
ProASICPLUS
Axcelerator
RTAX
SX-A
RTSX-S
Core Deliverables
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Netlist Version
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Compiled RTL Simulation Model, Compliant
with the Actel Libero™ Integrated Design
Environment (IDE)
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Compatible with the Actel Designer Place-and-
Route Tool
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RTL Version
VHDL or Verilog Core Source Code
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December 2005
v4.0
1
© 2005 Actel Corporation