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1553BBC-UR PDF预览

1553BBC-UR

更新时间: 2024-02-28 18:24:18
品牌 Logo 应用领域
ACTEL 总线控制器
页数 文件大小 规格书
30页 214K
描述
Core1553BBC MIL-STD-1553B Bus Controller

1553BBC-UR 数据手册

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Core1553BBC MIL-STD-1553B Bus Controller  
Synthesis Scripts  
Product Summary  
Actel-Developed Testbenches, VHDL and Verilog  
Intended Use  
Synthesis and Simulation Support  
1553B Bus Controller (BC)  
Synthesis: Synplicity®, Synopsys® (Design Compiler®/  
FPGA CompilerTM/FPGA ExpressTM), ExemplarTM  
DMA Backend Interface to External Memory  
Simulation: Vital-Compliant VHDL Simulators and  
OVI-Compliant Verilog Simulators  
Key Features  
Supports MIL-STD-1553B  
Interfaces to External RAM  
Verification and Compliance  
Supports up to 128kbytes of Memory  
Actel-Developed Simulation Testbench  
Synchronous  
Interface  
or  
Asynchronous  
Backend  
Core Implemented on the 1553B BC Development  
System  
Backend Interface Identical to Core1553BRT  
Third-Party 1553B Compliance Testing of the  
1553B Encoder and Decoder Blocks Implemented  
in an A54SXA32-STD Device  
Selectable Clock Rate of 12, 16, 20, or 24 MHz  
Provides Direct CPU Access to Memory  
Interfaces to Standard 1553B Transceivers  
Fully Automated Message Scheduling  
Development System (Optional)  
Frame Support  
Complete 1553B BC Implementation in an SX-A  
Device  
Conditional Branching and Sub-routines  
Variable Inter-message Gaps and RT Response  
Times  
Includes a PCI Interface for Host CPU Connection  
Includes Transceivers and Bus Termination  
Components  
Real Time Clock for Message Scheduling  
Asynchronous Message Support  
Contents  
Supported Families  
Fusion  
General Description ................................................... 2  
Core1553BBC Device Requirements .......................... 4  
Core1553BBC Verification and Compliance .............. 4  
MIL-STD-1553B Bus Overview .................................... 4  
I/O Signal Descriptions ............................................. 6  
Bus Transceivers ........................................................ 20  
Development System ............................................... 20  
Typical BC System ..................................................... 22  
Specifications ............................................................ 24  
Ordering Information .............................................. 28  
List of Changes ......................................................... 29  
Datasheet Categories ............................................... 29  
ProASIC3/E  
ProASICPLUS  
Axcelerator  
RTAX  
SX-A  
RTSX-S  
Core Deliverables  
Netlist Version  
Compiled RTL Simulation Model, Compliant  
with the Actel Libero™ Integrated Design  
Environment (IDE)  
Compatible with the Actel Designer Place-and-  
Route Tool  
RTL Version  
VHDL or Verilog Core Source Code  
December 2005  
v4.0  
1
© 2005 Actel Corporation  

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