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14539-00

更新时间： 2024-09-24 06:17:07

品牌	Logo	应用领域
CLARE		接口集成电路驱动
页数	文件大小	规格书
20页	2392K
描述
200-Column Cholesteric LCD Driver

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14539-00 数据手册

MXED401

200-Column Cholesteric LCD Driver

FEATURES:

OVERVIEW:

• Drives Reflective-type Liquid Crystal

Displays

• Black-White or Gray-Scale

• Cholesteric LCD (ChLCD) Compatible

• 200 Output Channels, Cascadeable

• 192-Channel Mode

Clare introduces the MXED401, targeted

for the emerging non-volatile reflective LCD

market, specifically bi-stable and multi-stable

Cholesteric LCD’s. The MXED401 supports 200

phase-controlled voltage data outputs. This is

the first standard product driver for ChLCD display

panels.

• Token-Based Bi-directional Data

Transfer

• 6-Bit Data to support 64-Level

Gray-Scale

• ±2V to ±7V panel drive

• 4mA Minimum Source/Sink at ±7VOutput

Levels

• 2.5V to 5V logic supply

• 26 MHz clock frequency

• 4mA Minimum Source/Sink at ±7V Output

Levels

• Gold-Bumped Die @ 60 micron Output Pitch

FUNCTIONALDESCRIPTION:

The MXED401 driver functions as a level shifter with a resting state at ground potential. Proper

operation of the logic enables gray-scale capability. The output is a 128 Counter Clock (CCLK) event

where each channel is a low resistive switch to external symmetric (with respect to ground) voltage

supplies. Proper operation of the logic allows gray scale capability. The output is initially low (MV4)

from one to sixty-four CCLK times, then continuously high (PV4) for sixty-four CCLK times, returning

low for the balance of the 128 CCLK cycle (before returning to its quiescent value(VSS2)). The data

driver chip is manufactured in a high voltage (30 V) CMOS process andis available in gold-bumped-

die form.

The Token Bit Shift Register is used to control data latch timing for the Temporary Storage Register.

A token bit (initialized by SRIN input) is transferred sequentially among the 200 possible (internal)

outputs of the Shift register. This allows data to fill the Temporary Storage Register to in a Right to

Left fashion. When the Temporary Register is filled its contents may be transferred to the Output

Storage register via the LAT input. Output phase control is then accomplished by the Pulse Phase

Shift Logic, data then passes to the High Voltage Translator unit to control the three output switches

associated with each column output driver.

14580

www.clare.com

January 29, 2003

12 3 4 5 6 7...20

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