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1430G5(NETLIGHT)

更新时间: 2024-02-05 04:26:21
品牌 Logo 应用领域
杰尔 - AGERE 时钟
页数 文件大小 规格书
10页 220K
描述
Type SONET/SDH Long-Reach Transceivers with Clock Recovery

1430G5(NETLIGHT) 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Transferred包装说明:,
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.42JESD-30 代码:R-PDFO-P
JESD-609代码:e0功能数量:1
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:FIBER OPTIC峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified标称供电电压:3.3 V
表面贴装:NO电信集成电路类型:ATM/SONET/SDH TRANSCEIVER
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:PIN/PEG端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

1430G5(NETLIGHT) 数据手册

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NetLight 1430G5 Type SONET/SDH  
Long-Reach Transceivers with Clock Recovery  
Data Sheet, Rev 1.  
August 2001  
its performance. Excessive ringing due to reflections  
caused by improperly terminated signal lines makes it  
difficult for the component receiving these signals to  
decipher the proper logic levels and can cause transi-  
tions to occur where none were intended. Also, by min-  
imizing high-frequency ringing, possible EMI problems  
can be avoided.  
Application Information (continued)  
Noise that couples into the receiver through the power  
supply pins can also degrade performance. It is  
recommended that the pi filter, shown in Figure 3, be  
used for both the transmitter and receiver power  
supplies.  
The signal-detect output is LVTTL logic. A logic low at  
this output indicates that the optical signal into the  
receiver has been interrupted or that the light level has  
fallen below the minimum signal detect threshold. This  
output should not be used as an error rate indicator,  
since its switching threshold is determined only by the  
magnitude of the incoming optical signal.  
Data, Clock, and Signal Detect Outputs  
The data, clock, and signal detect outputs of the 1430  
transceiver are driven by open-emitter NPN transistors,  
which have an output impedance of approximately 7 .  
Each output can provide approximately 50 mA maxi-  
mum current to a 50 load terminated to VCC – 2.0 V.  
Transceiver Processing  
Due to the high switching speeds of ECL outputs,  
transmission line design must be used to interconnect  
components. To ensure optimum signal fidelity, both  
data outputs (RD+/RD–) and clock outputs  
(CLK+/CLK–) should be terminated identically. The sig-  
nal lines connecting the data clock outputs to the next  
device should be equal in length and have matched  
impedances. Controlled impedance stripline or micro-  
strip construction must be used to preserve the quality  
of the signal into the next component and to minimize  
reflections back into the receiver, which could degrade  
The transceiver and plug can withstand normal wave  
soldering and aqueous spray cleaning processes.  
However, the transceiver is not hermetic, and should  
not be subjected to immersion in cleaning solvents.  
The transceiver case should not be exposed to temper-  
atures in excess of 125 °C. The fiber pigtail cannot  
exceed 85 °C. The transceiver pins can be wave sol-  
dered at 250 °C for up to 10 seconds.  
Transceiver Optical and Electrical Characteristics  
Table 2. Transmitter Optical and Electrical Characteristics (TC = –40 °C to +85 °C; VCC = 3.135 V—3.465 V)  
Parameter  
Symbol  
Min  
Max  
Unit  
Average Optical Output Power L-1.1  
Optical Wavelength L-1.1  
Spectral Width  
PO  
λC  
–5.0  
1280  
0
1335  
1
dBm  
nm  
nm  
dB  
∆λ20  
SMSR  
EXT  
ICCT  
Side-mode Suppression Ratio  
Dynamic Extinction Ratio  
Power Supply Current  
30  
10  
dB  
200  
mA  
Input Data Voltage:  
Low  
High  
VIL  
VIH  
VCC – 1.810 VCC – 1.475  
VCC – 1.165 VCC – 0.880  
V
V
Transmit Disable Voltage  
Transmit Enable Voltage  
Laser Bias Voltage  
VD  
VEN  
VBIAS  
VBF  
VCC – 1.165  
VCC  
VEE + 0.8  
0.70  
V
V
V
V
VEE  
0
Laser Back-facet Monitor Voltage  
0.01  
0.20  
4
Agere Systems Inc.  

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