Datasheet > 1430G5(NETLIGHT)

1430G5(NETLIGHT)

更新时间： 2024-02-06 20:43:14

品牌	Logo	应用领域
杰尔 - AGERE		时钟
页数	文件大小	规格书
10页	220K
描述
Type SONET/SDH Long-Reach Transceivers with Clock Recovery

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1430G5(NETLIGHT) 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Transferred	包装说明：	,
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.42	JESD-30 代码：	R-PDFO-P
JESD-609代码：	e0	功能数量：	1
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装形状：	RECTANGULAR
封装形式：	FIBER OPTIC	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	标称供电电压：	3.3 V
表面贴装：	NO	电信集成电路类型：	ATM/SONET/SDH TRANSCEIVER
温度等级：	INDUSTRIAL	端子面层：	TIN LEAD
端子形式：	PIN/PEG	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	Base Number Matches：	1

1430G5(NETLIGHT) 数据手册

NetLight 1430G5 Type SONET/SDH

Long-Reach Transceivers with Clock Recovery

Data Sheet, Rev 1.

August 2001

Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-

lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess

of those given in the operations sections of the data sheet. Exposure to absolute maximum ratings for extended

periods can adversely affect device reliability.

Parameter

Symbol

Min

Max

Unit

Supply Voltage

VCC

T^stg

—

3.6

°C

Operating Case Temperature Range

Storage Case Temperature Range

Lead Soldering Temperature/Time

Operating Wavelength Range

–40

—

°C

250/10

1.6

°C/s

1.1

Pin Information

20 19 18 17 16 15 14 13 12 11

20-PIN MODULE - TOP VIEW

2 3 4 5 6 7 8 9 10

1-967(F).b

Figure 1. 1430G5 and 1430H5-Type Transceivers, 20-Pin Configuration, Top View

Table 1. Transceiver Pin Descriptions

Number

Logic

Family

Symbol

Name/Description

Receiver

Mounting Studs. The mounting studs are provided for transceiver mechani-

cal attachment to the circuit board. They may also provide an optional con-

nection of the transceiver to the equipment chassis ground.

Photode- Photodetector Bias. This lead supplies bias for the PIN photodetector diode.

tector Bias

VEER

CLK–

Receiver Signal Ground.

Received Recovered Clock Out. The rising edge occurs at the rising edge of LVPECL

the received data output. The falling edge occurs in the middle of the received

data bit period.

CLK+

Received Recovered Clock Out. The falling edge occurs at the rising edge

of the received data output. The rising edge occurs in the middle of the

received data bit period.

LVPECL

VEER

VCCR

Receiver Signal Ground.

Receiver Power Supply.

Signal Detect.

LVTTL

Normal operation: logic one output.

Fault condition: logic zero output.

RD–

RD+

Received DATA Out. No Internal terminations will be provided.

Received DATA Out. No internal terminations will be provided.

LVPECL

Agere Systems Inc.

123 4 5 6 7...10

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