Datasheet > 微控制器和处理器 > 计时器或实时时钟> 1339-31DCGI8

1339-31DCGI8

更新时间： 2024-02-27 16:29:11

品牌	Logo	应用领域
艾迪悌 - IDT		计时器或实时时钟微控制器和处理器外围集成电路光电二极管
页数	文件大小	规格书
27页	362K
描述
REAL-TIME CLOCK WITH SERIAL I2C INTERFACE

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技术参数
数据手册

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1339-31DCGI8 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	SOIC-8	针数：	8
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.13
最大时钟频率：	0.032 MHz	信息访问方法：	I2C
中断能力：	Y	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3	长度：	4.9 mm
湿度敏感等级：	1	端子数量：	8
计时器数量：	1	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260	电源：	3.6/5 V
认证状态：	Not Qualified	座面最大高度：	1.75 mm
子类别：	Timer or RTC	最大供电电压：	5.5 V
最小供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn) - annealed	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
最短时间：	SECONDS	处于峰值回流温度下的最长时间：	30
易失性：	YES	宽度：	3.9 mm
uPs/uCs/外围集成电路类型：	TIMER, REAL TIME CLOCK	Base Number Matches：	1

1339-31DCGI8 数据手册

IDT1339

REAL-TIME CLOCK WITH SERIAL I²C INTERFACE

RTC

ESR (Effective Series Resistance)

PCB Layout

Choose the crystal with lower ESR. A low ESR helps the

crystal to start up and stabilize to the correct output

frequency faster compared to high ESR crystals.

Frequency Tolerance

The frequency tolerance for 32 KHz crystals should be

specified at nominal temperature (+25°C) on the crystal

manufacturer datasheet. The crystals used with IDT1338

typically have a frequency tolerance of 20ppm at +25°C.

1339

Specifications for a typical 32 kHz crystal used with our

device are shown in the table below.

PCB Assembly, Soldering and Cleaning

Board-assembly production process and assembly quality

can affect the performance of the 32 kHz oscillator.

Depending on the flux material used, the soldering process

can leave critical residues on the PCB surface. High

humidity and fast temperature cycles that cause humidity

condensation on the printed circuit board can create

process residuals. These process residuals cause the

insulation of the sensitive oscillator signal lines towards

each other and neighboring signals on the PCB to decrease.

High humidity can lead to moisture condensation on the

surface of the PCB and, together with process residuals,

reduce the surface resistivity of the board. Flux residuals on

the board can cause leakage current paths, especially in

humid environments. Thorough PCB cleaning is therefore

highly recommended in order to achieve maximum

performance by removing flux residuals from the board after

assembly. In general, reduction of losses in the oscillator

circuit leads to better safety margin and reliability.

Parameter

Nominal Freq.

Symbol Min

Typ

Max Units

f_O

ESR

C_L

32.768

kHz

Series Resistance

Load Capacitance

kΩ

PCB Design Consideration

•

Signal traces between IDT device pins and the crystal

must be kept as short as possible. This minimizes

parasitic capacitance and sensitivity to crosstalk and

EMI. Note that the trace capacitances play a role in the

effective crystal load capacitance calculation.

•

Data lines and frequently switching signal lines should be

routed as far away from the crystal connections as

possible. Crosstalk from these signals may disturb the

oscillator signal.

•

Reduce the parasitic capacitance between X1 and X2

signals by routing them as far apart as possible.

Power Control

The oscillation loop current flows between the crystal and

the load capacitors. This signal path (crystal to CL1 to

CL2 to crystal) should be kept as short as possible and

ideally be symmetric. The ground connections for both

capacitors should be as close together as possible.

Never route the ground connection between the

capacitors all around the crystal, because this long

ground trace is sensitive to crosstalk and EMI.

The power-control function is provided by a precise,

temperature-compensated voltage reference and a

comparator circuit that monitors the V_CClevel. The device is

fully accessible and data can be written and read when V_CC

is greater than V_PF. However, when V_CCfalls below V_PF, the

internal clock registers are blocked from any access. If V_PF

is less than V_BACKUP, the device power is switched from V_CC

to V_BACKUPwhen V_CCdrops below V_PF. If V_PFis greater than

V_BACKUP, the device power is switched from V_CCto V_BACKUP

when V_CCdrops below V_BACKUP. The registers are

maintained from the V_BACKUPsource until V_CCis returned to

nominal levels (Table 1). After V_CCreturns above V_PF, read

and write access is allowed after t_REC(see the

•

To reduce the radiation / coupling from oscillator circuit,

an isolated ground island on the GND layer could be

made. This ground island can be connected at one point

to the GND layer. This helps to keep noise generated by

the oscillator circuit locally on this separated island. The

ground connections for the load capacitors and the

oscillator should be connected to this island.

“Power-Up/Down Timing” diagram).

IDT® REAL-TIME CLOCK WITH SERIAL I²C INTERFACE

IDT1339

REV K 032910

1 2 345 6 7...27

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