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1339-31DCGI8

更新时间： 2024-02-10 11:56:05

品牌	Logo	应用领域
艾迪悌 - IDT		计时器或实时时钟微控制器和处理器外围集成电路光电二极管
页数	文件大小	规格书
27页	362K
描述
REAL-TIME CLOCK WITH SERIAL I2C INTERFACE

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技术参数
数据手册

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1339-31DCGI8 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	SOIC-8	针数：	8
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.13
最大时钟频率：	0.032 MHz	信息访问方法：	I2C
中断能力：	Y	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3	长度：	4.9 mm
湿度敏感等级：	1	端子数量：	8
计时器数量：	1	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260	电源：	3.6/5 V
认证状态：	Not Qualified	座面最大高度：	1.75 mm
子类别：	Timer or RTC	最大供电电压：	5.5 V
最小供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn) - annealed	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
最短时间：	SECONDS	处于峰值回流温度下的最长时间：	30
易失性：	YES	宽度：	3.9 mm
uPs/uCs/外围集成电路类型：	TIMER, REAL TIME CLOCK	Base Number Matches：	1

1339-31DCGI8 数据手册

IDT1339

REAL-TIME CLOCK WITH SERIAL I²C INTERFACE

RTC

Time and Date Operation

Alarms

The time and date information is obtained by reading the

appropriate register bytes. Table 3 shows the RTC registers.

The time and date are set or initialized by writing the

appropriate register bytes. The contents of the time and

date registers are in the BCD format. The IDT1339 can be

run in either 12-hour or 24-hour mode. Bit 6 of the hours

When high, the 12-hour mode is selected. In the 12-hour

mode, bit 5 is the AM/PM bit with logic high being PM. In the

24-hour mode, bit 5 is the second 10-hour bit (20 to 23

hours). All hours values, including the alarms, must be

re-entered whenever the 12/24-hour mode bit is changed.

The century bit (bit 7 of the month register) is toggled when

the years register overflows from 99 to 00. The day-of-week

the day of week are user-defined, but must be sequential

(i.e., if 1 equals Sunday, then 2 equals Monday and so on).

Illogical time and date entries result in undefined operation.

The IDT1339 contains two time of day/date alarms. Alarm 1

can be set by writing to registers 07h to 0Ah. Alarm 2 can be

set by writing to registers 0Bh to 0Dh. The alarms can be

programmed (by the Alarm Enable and INTCN bits of the

Control Register) to activate the SQW/INT output on an

alarm match condition. Bit 7 of each of the time of day/date

alarm registers are mask bits (Table 4). When all the mask

bits for each alarm are logic 0, an alarm only occurs when

the values in the timekeeping registers 00h to 06h match the

values stored in the time of day/date alarm registers. The

alarms can also be programmed to repeat every second,

minute, hour, day, or date. Table 4 shows the possible

settings. Configurations not listed in the table result in

illogical operation.

The DY/DT bits (bit 6 of the alarm day/date registers) control

whether the alarm value stored in bits 0 to 5 of that register

reflects the day of the week or the date of the month. If

DY/DT is written to a logic 0, the alarm is the result of a

match with date of the month. If DY/DT is written to a logic

1, the alarm is the result of a match with day of the week.

When reading or writing the time and date registers,

secondary (user) buffers are used to prevent errors when

the internal registers update. When reading the time and

date registers, the user buffers are synchronized to the

internal registers on any start or stop, and when the address

pointer rolls over to zero. The countdown chain is reset

whenever the seconds register is written. Write transfers

occurs on the acknowledge pulse from the device. To avoid

rollover issues, once the countdown chain is reset, the

remaining time and date registers must be written within one

second. If enabled, the 1 Hz square-wave output transitions

high 500 ms after the seconds data transfer, provided the

oscillator is already running.

The device checks for an alarm match once per second.

When the RTC register values match alarm register

settings, the corresponding Alarm Flag ‘A1F’ or ‘A2F’ bit is

set to logic 1. If the corresponding Alarm Interrupt Enable

‘A1IE’ or ‘A2IE’ is also set to logic 1 and the INTCN bit is set

to logic 1, the alarm condition activates the SQW/INT signal.

If the BBSQI bit is set to 1, the INT output activates while the

part is being powered by V_BACKUP. The alarm output

remains active until the alarm flag is cleared by the user.

IDT® REAL-TIME CLOCK WITH SERIAL I²C INTERFACE

IDT1339

REV K 032910

1...4 5 678 9 10...27

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