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1337GDCGK8 PDF预览

1337GDCGK8

更新时间: 2024-02-23 10:16:35
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路
页数 文件大小 规格书
28页 278K
描述
Real Time Clock, 1 Timer(s), PDSO8, 0.150 INCH, ROHS COMPLIANT, SOIC-8

1337GDCGK8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:0.150 INCH, ROHS COMPLIANT, SOIC-8针数:8
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.65
最大时钟频率:0.4 MHz信息访问方法:I2C
中断能力:YJESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:4.9 mm
湿度敏感等级:1位数:8
端子数量:8计时器数量:1
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:2/5 V认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Timer or RTC
最大供电电压:5.5 V最小供电电压:1.8 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
最短时间:SECONDS处于峰值回流温度下的最长时间:30
宽度:3.9 mmuPs/uCs/外围集成电路类型:TIMER, REAL TIME CLOCK
Base Number Matches:1

1337GDCGK8 数据手册

 浏览型号1337GDCGK8的Datasheet PDF文件第2页浏览型号1337GDCGK8的Datasheet PDF文件第3页浏览型号1337GDCGK8的Datasheet PDF文件第4页浏览型号1337GDCGK8的Datasheet PDF文件第6页浏览型号1337GDCGK8的Datasheet PDF文件第7页浏览型号1337GDCGK8的Datasheet PDF文件第8页 
IDT1337G  
REA LTIME CLOCK WITH SERIAL INTERFACE  
RTC  
Note: IDT1337CSRI integrates a standard 32.768 kHz  
crystal in the package and contributes an additional  
frequency error of 10ppm at nominal VCC (+3.3 V) and  
TA=+25°C.  
to the GND layer. This helps to keep noise generated by  
the oscillator circuit locally on this separated island. The  
ground connections for the load capacitors and the  
oscillator should be connected to this island.  
ESR (Effective Series Resistance)  
PCB Layout  
Choose the crystal with lower ESR. A low ESR helps the  
crystal to start up and stabilize to the correct output  
frequency faster compared to high ESR crystals.  
Frequency Tolerance  
The frequency tolerance for 32 KHz crystals should be  
specified at nominal temperature (+25°C) on the crystal  
manufacturer datasheet. The crystals used with IDT1337G  
typically have a frequency tolerance of +/-20ppm at +25°C.  
1337G  
Specifications for a typical 32 kHz crystal used with our  
device are shown in the table below.  
Parameter  
Nominal Freq.  
Symbol Min  
Typ  
Max Units  
PCB Assembly, Soldering and Cleaning  
Board-assembly production process and assembly quality  
can affect the performance of the 32 KHz oscillator.  
Depending on the flux material used, the soldering process  
can leave critical residues on the PCB surface. High  
humidity and fast temperature cycles that cause humidity  
condensation on the printed circuit board can create  
process residuals. These process residuals cause the  
insulation of the sensitive oscillator signal lines towards  
each other and neighboring signals on the PCB to decrease.  
High humidity can lead to moisture condensation on the  
surface of the PCB and, together with process residuals,  
reduce the surface resistivity of the board. Flux residuals on  
the board can cause leakage current paths, especially in  
humid environments. Thorough PCB cleaning is therefore  
highly recommended in order to achieve maximum  
performance by removing flux residuals from the board after  
assembly. In general, reduction of losses in the oscillator  
circuit leads to better safety margin and reliability.  
fO  
ESR  
CL  
32.768  
kHz  
Series Resistance  
Load Capacitance  
80  
k  
7
pF  
PCB Design Consideration  
Signal traces between IDT device pins and the crystal  
must be kept as short as possible. This minimizes  
parasitic capacitance and sensitivity to crosstalk and  
EMI. Note that the trace capacitances play a role in the  
effective crystal load capacitance calculation.  
Data lines and frequently switching signal lines should be  
routed as far away from the crystal connections as  
possible. Crosstalk from these signals may disturb the  
oscillator signal.  
Reduce the parasitic capacitance between X1 and X2  
signals by routing them as far apart as possible.  
The oscillation loop current flows between the crystal and  
the load capacitors. This signal path (crystal to CL1 to  
CL2 to crystal) should be kept as short as possible and  
ideally be symmetric. The ground connections for both  
capacitors should be as close together as possible.  
Never route the ground connection between the  
capacitors all around the crystal, because this long  
ground trace is sensitive to crosstalk and EMI.  
To reduce the radiation / coupling from oscillator circuit,  
an isolated ground island on the GND layer could be  
made. This ground island can be connected at one point  
2
IDT® REAL-TIME CLOCK WITH I C SERIAL INTERFACE  
5
IDT1337G  
REV L 062613  

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