Datasheet > 125932-HMC674LC3C

125932-HMC674LC3C

更新时间： 2022-02-26 12:46:18

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
14页	330K
描述
9.3 GHz Latched Comparator

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Data Sheet

HMC674LC3C/HMC674LP3E

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

VTP 1

INP 2

INN 3

VTN 4

12 V

CCO

VTP 1

INP 2

INN 3

VTN 4

12 V

CCO

HMC674LC3C

11 Q

10 Q

HMC674LP3E

11 Q

10 Q

TOP VIEW

(Not to Scale)

CCO

PACKAGE

BASE

PACKAGE

BASE

NOTES

1. NIC = NOT INTERNALLY CONNECTED. CONNECT

THIS PIN TO GROUND FOR IMPROVED NOISE.

2. EXPOSED PAD. THE EXPOSED PAD MUST BE

1. NIC = NOT INTERNALLY CONNECTED. CONNECT

THIS PIN TO GROUND FOR IMPROVED NOISE.

2. EXPOSED PAD. THE EXPOSED PAD MUST BE

CONNECTED TO V

Figure 3. HMC674LC3C Pin Configuration

Figure 4. HMC674LP3E Pin Configuration

Table 8. HMC674LC3C/HMC674LP3E Pin Function Descriptions

Pin No.

Mnemonic Description

5, 16

VTP

INP

INN

VTN

V_CCI

Termination Resistor Return Pin for V_PInput. See Figure 5 for the interface schematic.

Noninverting Analog Input. See Figure 5 for the interface schematic.

Inverting Analog Input. See Figure 5 for the interface schematic.

Termination Resistor Return Pin for V_NInput. See Figure 5 for the interface schematic.

Positive Supply Voltage Input Stage. See Figure 6 for the interface schematic.

Latch Enable Input Pin, Inverting Side. See the Theory of Operation section for additional information. See

Figure 6 for the interface schematic.

Latch Enable Input Pin, Noninverting Side. See the Theory of Operation section for additional information. See

Figure 6 for the interface schematic.

9, 12

NIC

V_CCO

Not Internally Connected. Connect this pin to ground for improved noise.

Positive Supply Voltage for the Output Stage. See Figure 7 for the interface schematic.

Inverting Output. Q is at logic low if the analog voltage at the noninverting input, INP, is greater than the

analog voltage at the inverting input, INN, provided that the comparator is in track mode. See the Theory of

Operation section for additional information. See Figure 7 for the interface schematic.

Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, INP, is greater than the

analog voltage at the inverting input, INN, provided that the comparator is in track mode. See the Theory of

Operation section for additional information. See Figure 7 for the interface schematic.

V_EE

HYS

Negative Power Supply, −3 V. See Figure 6 for the interface schematic.

Hysteresis Control Pin. Leave this pin disconnected for zero hysteresis. Connect this pin to V_EEwith a resistor to add

the desired amount of hysteresis. See Figure 12 to determine the correct size of the R_HYShysteresis control resistor.

See Figure 8 for the interface schematic.

RTN

Return for ESD Protection.

EPAD

Exposed Pad. The exposed pad must be connected to V_EE.

Rev. K | Page 7 of 14

1...4 5 678 9 10...14

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