Datasheet > 11C91DM

11C91DM

更新时间： 2024-02-18 19:28:43

品牌	Logo	应用领域
其他 - ETC		预分频器逻辑集成电路时钟
页数	文件大小	规格书
10页	158K
描述
Prescaler/Frequency Divider

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技术参数
数据手册

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11C91DM 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	包装说明：	DIP, DIP16,.3
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.92	JESD-30 代码：	R-XDIP-T16
JESD-609代码：	e0	逻辑集成电路类型：	PRESCALER
湿度敏感等级：	2A	端子数量：	16
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	CERAMIC	封装代码：	DIP
封装等效代码：	DIP16,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	250
认证状态：	Not Qualified	筛选级别：	MIL-STD-883 Class C
子类别：	Prescaler/Multivibrators	表面贴装：	NO
技术：	ECL	温度等级：	MILITARY
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	Base Number Matches：	1

11C91DM 数据手册

Functional Description

The 11C90 contains four ECL Flip-Flops, an ECL to TTL

converter and a Schottky TTL output buffer with an active

pull-up. Three of the Flip-Flops operate as a synchronous

shift counter driving the fourth Flip-Flop operating as an

asynchronous toggle. The internal feedback logic is such

that the TTL output and the Q ECL output are HIGH for six

clock periods and LOW for five clock periods. The Mode

Control (M) inputs can modify the feedback to make the

output HIGH for five clock periods and LOW for five clock

periods, as indicated in the Count Sequence Table.

TL/F/9892–10

The feedback logic is such that the instant the output goes

HIGH, the circuit is already committed as to whether the

output period will be 10 or 11 clock periods long. This

means that subsequent changes in an M input signal, in-

cluding decoding spikes, will have no effect on the current

output period. The only timing restriction for an M input sig-

nal is that it be in the desired state at least a setup time

before the clock that follows the HHLL state shown in the

table. The allowable propagation delay through external log-

ic to an M input is maximized by designing it to use the

positive transition of the 11C90 output as its active edge.

This gives an allowable delay of ten clock periods, minus

the CP to Q delay of the 11C90 and the M to CP setup time.

If the external logic uses the negative output transition as its

active edge, the allowable delay is reduced to five clock

periods minus the previously mentioned delay and setup

time.

FIGURE 3. Capacitively Coupled Clocking

TL/F/9892–11

100

162

261

R X

80.6

130

121

196

R X

Capacitively coupled triggering is simplified by the 400X re-

sistor which connects pin 15 to the internal V reference.

e b

2.0V

5.2V, V

0V, V

By connecting this to the CP input, as shown inFigure 3, the

clock is automatically centered about the input threshold. A

clock duty cycle of 50% provides the fastest operation,

since the Flip-Flops are Master-Slave types with offset clock

thresholds between master and slave. This feature ensures

that the circuit will operate with clock waveforms having

very slow rise and fall times, and thus, there is no maximum

frequency restriction. Recommended minimum and maxi-

mum clock amplitude as a function of a frequency and tem-

perature are shown in the graph labeled Figure 2. When the

CP or any other input is driven from another ECL circuit,

normal ECL termination methods are recommended. One

method is indicated in Figure 4. Other ECL termination

methods are discussed in the F100K ECL Design Guide

(Section 5 of Databook).

FIGURE 4. Clocking by ECL Source via Terminated Line

When an M input is to be driven from a TTL output operating

and ground (V ), the internal 2 kX

from the same V

resistor can be used to pull the TTL output up as shown in

Figure 5. Some types of TTL outputs will only pull up to

within two diode drops of V , which is not high enough for

11C90 inputs. The resistor will pull the signal up through the

threshold region, although this final rise may be somewhat

slow, depending on wiring capacitance. A resistor network

that gives faster rise and also lower impedance is shown in

Figure 6.

TL/F/9892–12

FIGURE 5. Using Internal Pull-Up with TTL Source

TL/F/9892–13

TL/F/9892–5

FIGURE 6. Faster Low Impedance TTL to ECL Interface

FIGURE 2. AC Coupled Triggering Characteristics

1...3 4 567 8 9 10

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