Datasheet > 存储 > EEPROM> 11AA020-E/MNY

11AA020-E/MNY

更新时间： 2024-02-14 01:30:15

品牌	Logo	应用领域
美国微芯 - MICROCHIP		可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
38页	571K
描述
1K-16K UNI/O® Serial EEPROM Family Data Sheet

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11AA020-E/MNY 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	TO-92
包装说明：	ROHS COMPLIANT, PLASTIC, TO-92, 3 PIN	针数：	3
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.51	风险等级：	5.59
最大时钟频率 (fCLK)：	1 MHz	JESD-30 代码：	X-PBCY-T3
JESD-609代码：	e3	内存密度：	2048 bit
内存集成电路类型：	EEPROM	内存宽度：	8
功能数量：	1	端子数量：	3
字数：	256 words	字数代码：	256
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	256X8
封装主体材料：	PLASTIC/EPOXY	封装代码：	TO-92
封装形状：	UNSPECIFIED	封装形式：	CYLINDRICAL
并行/串行：	SERIAL	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	串行总线类型：	1-WIRE
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	1.8 V
标称供电电压 (Vsup)：	5 V	表面贴装：	NO
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	MATTE TIN	端子形式：	THROUGH-HOLE
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
最长写入周期时间 (tWC)：	10 ms	Base Number Matches：	1

11AA020-E/MNY 数据手册

11AAXXX/11LCXXX

3.8.1

FREQUENCY DRIFT

3.6

Device Standby

Within a system, there is a possibility that frequencies

can drift due to changes in voltage, temperature, etc.

The re-synchronization circuitry provides some toler-

ance for such frequency drift. The tolerance range is

specified by two parameters, FDRIFT and FDEV. FDRIFT

specifies the maximum tolerable change in bus fre-

quency per byte. FDEV specifies the overall limit in fre-

quency deviation within an operation (i.e., from the end

of the start header until communication is terminated

for that operation). The start header at the beginning of

the next operation will reset the re-synchronization cir-

cuitry and allow for another FDEV amount of frequency

drift.

The 11XX features a low-power Standby mode during

which the device is waiting to begin a new command.

A high-to-low transition on SCIO will exit low-power

mode and prepare the device for receiving the start

header.

Standby mode will be entered upon the following

conditions:

• A NoMAK followed by a SAK (i.e., valid termina-

tion of a command)

• Reception of a standby pulse

Note: In the case of the WRITE, WRSR, SETAL, or

ERALcommands, the write cycle is initiated

upon receipt of the NoMAK, assuming all

other write requirements have been met.

3.8.2

EDGE JITTER

Ensuring that edge transitions from the master always

occur exactly in the middle or end of the bit period is not

always possible. Therefore, the re-synchronization cir-

cuitry is designed to provide some tolerance for edge

jitter.

3.7

Device Idle

The 11XX features an Idle mode during which all serial

data is ignored until a standby pulse occurs. Idle mode

will be entered upon the following conditions:

The 11XX adjusts its phase every MAK bit, so TIJIT

specifies the maximum allowable peak-to-peak jitter

relative to the previous MAK bit. Since the position of

the previous MAK bit would be difficult to measure by

the master, the minimum and maximum jitter values for

a system should be considered the worst-case. These

values will be based on the execution time for different

branch paths in software, jitter due to thermal noise,

etc.

• Invalid device address

• Invalid command byte, including Read, CRRD,

Write, WRSR, SETAL and ERAL during a write

cycle.

• Missed edge transition

• Reception of a MAK following a WREN, WRDI,

SETAL, or ERALcommand byte

• Reception of a MAK following the data byte of a

The difference between the minimum and maximum

values, as a percentage of the bit period, should be cal-

culated and then compared against TIJIT to determine

jitter compliance.

WRSRcommand

An invalid start header will indirectly cause the device

to enter Idle mode. Whether or not the start header is

invalid cannot be detected by the slave, but will

prevent the slave from synchronizing properly with the

master. If the slave is not synchronized with the

master, an edge transition will be missed, thus causing

the device to enter Idle mode.

Note: Because the 11XX only re-synchronizes

during the MAK bit, the overall ability to

remain synchronized depends on a combi-

nation of frequency drift and edge jitter (i.e.,

if the MAK bit edge is experiencing the max-

imum allowable edge jitter, then there is no

room for frequency drift). Conversely, if the

frequency has drifted to the maximum

amount tolerable within a byte, then no edge

jitter can be present.

3.8

Synchronization

At the beginning of every command, the 11XX utilizes

the start header to determine the master’s bus clock

period. This period is then used as a reference for all

subsequent communication within that command.

The 11XX features re-synchronization circuitry which

will monitor the position of the middle data edge during

each MAK bit and subsequently adjust the internal time

reference in order to remain synchronized with the

master.

There are two variables which can cause the 11XX to

lose synchronization. The first is frequency drift,

defined as a change in the bit period, TE. The second is

edge jitter, which is a single occurrence change in the

position of an edge within a bit period, while the bit

period itself remains constant.

Preliminary

DS22067E-page 9

1...6 7 8910 11 12...38

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