Datasheet > 1191

1191

更新时间： 2022-11-24 21:47:48

品牌	Logo	应用领域
美信 - MAXIM		/
页数	文件大小	规格书
27页	492K
描述
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC

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1191 数据手册

Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC

ELECTRICAL CHARACTERISTICS (continued)

= 3.0V, OV

= 1.8V, V

= V

(internal reference), C ≈ 10pF at digital outputs, f

= 7.5MHz, C

= C = C

REFN COM

REFIN

CLK

REFP

= 0.33µF, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

Normal operating mode, f = 1.875MHz

MIN

TYP

MAX

UNITS

4.0

5.0

at -0.5dB FS, CLK input from GND to V

Idle mode (tri-state), f = 1.875MHz at -

4.0

2.2

0.1

1.0

0.1

0.5dB FS, CLK input from GND to V

Analog Supply Current

Standby mode, CLK input from GND to

Shutdown mode, CLK = GND or V

PD0 = PD1 = OGND

5.0

µA

Normal operating mode,

= 1.875MHz at -0.5dB FS, C ≈ 10pF

Idle mode (tri-state), DC input, CLK =

GND or V PD0 = OV , PD1 = OGND

DD,

Digital Output Supply Current

(Note 3)

ODD

Standby mode, DC input, CLK = GND or

PD0 = OGND, PD1 = OV

µA

DD,

Shutdown mode, CLK = GND or V

PD0 = PD1 = OGND

TIMING CHARACTERISTICS

CLK Rise to CHA Output Data

Valid

50% of CLK to 50% of data, Figure 5

(Note 4)

8.5

DOA

DOB

DA/B

CLK Fall to CHB Output Data

Valid

50% of CLK to 50% of data, Figure 5

(Note 4)

CLK Rise/Fall to A/B Rise/Fall

Time

50% of CLK to 50% of A/B, Figure 5

(Note 4)

PD1 Rise to Output Enable

PD1 Fall to Output Disable

CLK Duty Cycle

PD0 = OV

DIS

CLK Duty-Cycle Variation

Wake-Up Time from Shutdown

Mode

(Note 5)

µs

WAKE, SD

Wake-Up Time from Standby

Mode

5.5

µs

WAKE, ST

Digital Output Rise/Fall Time

20% to 80%

INTERCHANNEL CHARACTERISTICS

= 1.875MHz at -0.5dB FS,

= 0.3MHz at -0.5dB FS (Note 6)

IN,X

Crosstalk Rejection

-75

IN,Y

Amplitude Matching

Phase Matching

= 1.875MHz at -0.5dB FS (Note 7)

0.03

Degrees

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1 2 3 456 7 8...27

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