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10TPB100M PDF预览

10TPB100M

更新时间： 2024-01-16 04:50:54
品牌 Logo 应用领域
德州仪器 - TI 稳压器电容器控制器
页数 文件大小 规格书
31页 1294K
描述
LM2727/LM2737 N-Channel FET Synchronous Buck Regulator Controller

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10TPB100M 技术参数

是否Rohs认证： 符合生命周期：Obsolete
包装说明：, 2917Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8532.21.00.50
风险等级：5.74其他特性：RIPPLE CURRENT MEASURED AT 100KHZ TO 500 KHZ
电容：100 µF电容器类型：TANTALUM CAPACITOR
介电材料：TANTALUM (SOLID POLYMER)高度：2.8 mm
JESD-609代码：e4漏电流：0.1 mA
长度：7.3 mm安装特点：SURFACE MOUNT
负容差：20%端子数量：2
最高工作温度：105 °C最低工作温度：-55 °C
封装形状：RECTANGULAR PACKAGE封装形式：SMT
极性：POLARIZED正容差：20%
额定（直流）电压（URdc）：10 V纹波电流：1900 mA
尺寸代码：2917表面贴装：YES
Delta切线：0.08端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形状：J BEND宽度：4.3 mm
Base Number Matches：1

10TPB100M 数据手册

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LM2727, LM2737  
SNVS205D –AUGUST 2002–REVISED MARCH 2013  
www.ti.com  
Connection Diagram  
1
2
3
4
5
6
7
14  
13  
12  
BOOT  
LG  
HG  
PGND  
PGND  
SGND  
Vcc  
SD  
11  
10  
9
FREQ  
FB  
SS  
PWGD  
ISEN  
8
EAO  
Figure 1. 14-Lead Plastic TSSOP  
θJA = 155°C/W  
See Package Number PW0014A  
PIN DESCRIPTION  
BOOT (Pin 1) - Supply rail for the N-channel MOSFET gate drive. The voltage should be at least one gate threshold above the regulator  
input voltage to properly turn on the high-side N-FET.  
LG (Pin 2) - Gate drive for the low-side N-channel MOSFET. This signal is interlocked with HG to avoid shoot-through problems.  
PGND (Pins 3, 13) - Ground for FET drive circuitry. It should be connected to system ground.  
SGND (Pin 4) - Ground for signal level circuitry. It should be connected to system ground.  
VCC (Pin 5) - Supply rail for the controller.  
PWGD (Pin 6) - Power Good. This is an open drain output. The pin is pulled low when the chip is in UVP, OVP, or UVLO mode. During  
normal operation, this pin is connected to VCC or other voltage source through a pull-up resistor.  
ISEN (Pin 7) - Current limit threshold setting. This sources a fixed 50µA current. A resistor of appropriate value should be connected  
between this pin and the drain of the low-side FET.  
EAO (Pin 8) - Output of the error amplifier. The voltage level on this pin is compared with an internally generated ramp signal to determine  
the duty cycle. This pin is necessary for compensating the control loop.  
SS (Pin 9) - Soft start pin. A capacitor connected between this pin and ground sets the speed at which the output voltage ramps up. Larger  
capacitor value results in slower output voltage ramp but also lower inrush current.  
FB (Pin 10) - This is the inverting input of the error amplifier, which is used for sensing the output voltage and compensating the control  
loop.  
FREQ (Pin 11) - The switching frequency is set by connecting a resistor between this pin and ground.  
SD (Pin 12) - IC Logic Shutdown. When this pin is pulled low the chip turns off the high side switch and turns on the low side switch. While  
this pin is low, the IC will not start up. An internal 20µA pull-up connects this pin to VCC  
.
HG (Pin 14) - Gate drive for the high-side N-channel MOSFET. This signal is interlocked with LG to avoid shoot-through problems.  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
2
Submit Documentation Feedback  
Copyright © 2002–2013, Texas Instruments Incorporated  
Product Folder Links: LM2727 LM2737  
1234567...31

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