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10AX066H2F34I2SG PDF预览

10AX066H2F34I2SG

更新时间： 2024-01-01 11:57:50
品牌 Logo 应用领域
英特尔 - INTEL 栅可编程逻辑
页数 文件大小 规格书
110页 1391K
描述
Field Programmable Gate Array, 660000-Cell, CMOS, PBGA1152, 35 X 35 MM, ROHS COMPLIANT, FBGA-1152

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10AX066H2F34I2SG 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：35 X 35 MM, ROHS COMPLIANT, FBGA-1152Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.41
JESD-30 代码：S-PBGA-B1152长度：35 mm
输入次数：492逻辑单元数量：660000
输出次数：492端子数量：1152
最高工作温度：100 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA1152,34X34,40封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：NOT SPECIFIED
电源：0.9 V可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified座面最大高度：3.65 mm
子类别：Field Programmable Gate Arrays最大供电电压：0.93 V
最小供电电压：0.87 V标称供电电压：0.9 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：35 mm
Base Number Matches：1

10AX066H2F34I2SG 数据手册

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A10-DATASHEET  
2015.12.31  
104  
Document Revision History  
Date  
Version  
Changes  
•
Added –I1S, –I2S, and –E2S speed grades to the following tables:  
•
•
•
•
•
Clock Tree Performance for Arria 10 Devices  
DSP Block Performance Specifications for Arria 10 Devices  
Memory Block Performance Specifications for Arria 10 Devices  
High-Speed I/O Specifications for Arria 10 Devices  
Memory Output Clock Jitter Specifications for Arria 10 Devices  
•
•
•
•
Updated fIN minimum value from 27 MHz to 50 MHz for all speed grades in the Fractional PLL Specifica‐  
tions for Arria 10 Devices table.  
Changed the description for fINPFD to "Input clock frequency to the PFD" in the I/O PLL Specifications for  
Arria 10 Devices table.  
Updated DSP Block Performance Specifications for Arria 10 Devices table for VCC and VCCP at 0.9 V typical  
value. Added DSP specifications for VCC and VCCP at 0.95 V typical value.  
Updated Ibias minimum value from 8 μA to 10 μA and maximum value from 200 μA to 100 μA in the  
External Temperature Sensing Diode Specifications for Arria 10 Devices table.  
Added DPA (soft CDR mode) specifications in High-Speed I/O Specifications for Arria 10 Devices table.  
Added description in POR Specifications section: Power-on reset (POR) delay is defined as the delay  
between the time when all the power supplies monitored by the POR circuitry reach the minimum  
recommended operating voltage to the time when the nSTATUSis released high and your device is ready to  
begin configuration.  
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•
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•
Moved the following timing diagrams to the Configuration, Design Security, and Remote System Upgrades  
in Arria 10 Devices chapter.  
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FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is 1  
FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is >1  
AS Configuration Timing Waveform  
PS Configuration Timing Waveform  
Removed the DCLK-to-DATA[] ratio when both encryption and compression are turned on. Added  
description to the table: You cannot turn on encryption and compression at the same time for Arria 10  
devices.  
Arria 10 Device Datasheet  
Send Feedback  
Altera Corporation  
1...101102103104105106107...110

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