Datasheet > 05F6919

05F6919

更新时间： 2022-01-19 07:38:00

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其他 - ETC		/
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7页	139K
描述
IC-MONOLITHIC MULTIPLIER

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05F6919 数据手册

AD532

ORDERING GUIDE

CHIP DIMENSIONS AND BONDING DIAGRAM

Contact factory for latest dimensions.

Temperature

Ranges

Package

Descriptions

Package

Options

Dimensions shown in inches and (mm).

Model

AD532JD

0°C to +70°C

–55°C to +125°C

Side Brazed DIP

Header

Chip

Side Brazed DIP

LCC

Header

D-14

H-10A

AD532JD/+

AD532KD

AD532KD/+

AD532JH

AD532KH

AD532J Chip

AD532SD

AD532SD/883B

JM38510/13903BCA –55°C to +125°C

AD532SE/883B

AD532SH

AD532SH/883B

D-14

E-20A

H-10A

–55°C to +125°C

JM38510/13903BIA –55°C to +125°C

AD532S Chip –55°C to +125°C

Header

Chip

FUNCTIONAL DESCRIPTION

The functional block diagram for the AD532 is shown in Figure

1, and the complete schematic in Figure 2. In the multiplying

and squaring modes, Z is connected to the output to close the

feedback around the output op amp. (In the divide mode, it is

used as an input terminal.)

The X and Y inputs are fed to high impedance differential am-

plifiers featuring low distortion and good common-mode rejec-

tion. The amplifier voltage offsets are actively laser trimmed

to zero during production. The product of the two inputs is

resolved in the multiplier cell using Gilbert’s linearized trans-

conductance technique. The cell is laser trimmed to obtain

V_OUT= (X₁– X₂)(Y₁– Y₂)/10 volts. The built-in op amp is used

to obtain low output impedance and make possible self-contained

operation. The residual output voltage offset can be zeroed at

V_OSin critical applications . . . otherwise the V_OSpin should be

grounded.

Figure 1. Functional Block Diagram

Figure 2. Schematic Diagram

–3–

REV. B

1 234 5 6 7

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