Datasheet > XF8250

XF8250

更新时间： 2024-09-30 19:51:59

品牌	Logo	应用领域
赛灵思 - XILINX		时钟数据传输外围集成电路
页数	文件大小	规格书
5页	36K
描述
Serial I/O Controller, 1 Channel(s), 0.0762939453125MBps, CMOS

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中文翻译

获取价格

技术参数
数据手册

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XF8250 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	compliant	HTS代码：	8542.31.00.01
风险等级：	5.77	地址总线宽度：	3
边界扫描：	NO	最大时钟频率：	10 MHz
最大数据传输速率：	0.0762939453125 MBps	外部数据总线宽度：	8
JESD-609代码：	e0	低功率模式：	NO
串行 I/O 数：	1	认证状态：	Not Qualified
技术：	CMOS	端子面层：	TIN LEAD
uPs/uCs/外围集成电路类型：	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	Base Number Matches：	1

XF8250 数据手册

XF8250 Asynchronous

Communications Core

September 16, 1999

Product Speciﬁcation

™

AllianceCORE Fact

Core Speciﬁcs

Device Family

XC4000E/XL

Spartan

CLBs

Core

Core+Ext logic

114

7810 South Hardy Drive, Suite 104

Tempe, Arizona 85284 USA

Phone: +1 888-845-5585 (USA)

+1 480-753-5585

CORE I/O

Core ¹

Core+Ext logic

Fax:

E-mail: info@memecdesign.com

URL: www.memecdesign.com

+1 480-753-5899

Systems Clock fmax

10+MHz

Device Features

Used

Tbufs, global clock buffers

Provided with Core

Features

Documentation

Core schematics, User’s guide,

Application notes, FAQ,

•

Compatible with Xilinx CORE Generator tool

Function compatible with Industry Standard 8250

Combined UART and Baud Rate Generator

DC to 625K baud (DC to 10 MHz Clock)

1 to 65535 divisor generates 16X clock

Prioritized interrupt mode

Microprocessor bus oriented interface

Modem interface Line break generation and detection

Loopback and Echo modes

Implementation instructions

Design File Formats

Verification Tool

.ngo netlist

Viewlogic, Foundation or Verilog

source files available extra

Machine-readable simulation

vectors for ViewLogic ViewSim,

Testbench for Foundation, VHDL

and Verilog.

Applications

Symbols

ViewLogic, Foundation

Instantiation templates for VHDL

and Verilog

•

Serial data communications applications

Logic consolidation

Constraint Files

.ucf

Evaluation Model

None

Reference designs &

application notes

Sample designs in Viewlogic,

Foundation, VHDL and Verilog

Additional Items

Warranty by MDS

Netlist only version available

on enCORE CD-ROM

Design Tool Requirements

Xilinx Core Tools

Alliance/Foundation 1.4

Support

Support provided by Memec Design Services.

Notes:

1. Assuming all core signals are routed off-chip.

2. Minimum guaranteed speed to meet industry standard

speciﬁcation

September 16, 1999

12 3 4 5

中文翻译

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