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XC8101M1250C PDF预览

XC8101M1250C

更新时间： 2024-02-12 09:54:41
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
116页 886K
描述
IC,DSP,16-BIT,CMOS,BGA,332PIN,PLASTIC

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XC8101M1250C 技术参数

生命周期：Obsolete包装说明：PLASTIC, FLIP CHIP, BGA-332
Reach Compliance Code：unknownECCN代码：3A001.A.3
HTS代码：8542.31.00.01风险等级：5.83
地址总线宽度：32桶式移位器：NO
边界扫描：YES最大时钟频率：62.5 MHz
外部数据总线宽度：64格式：FIXED POINT
内部总线架构：MULTIPLEJESD-30 代码：S-PBGA-B332
长度：17 mm低功率模式：YES
端子数量：332封装主体材料：PLASTIC/EPOXY
封装代码：FBGA封装形状：SQUARE
封装形式：GRID ARRAY, FINE PITCH认证状态：Not Qualified
座面最大高度：2.6 mm最大供电电压：1.7 V
最小供电电压：1.5 V标称供电电压：1.6 V
表面贴装：YES端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
宽度：17 mmuPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：1

XC8101M1250C 数据手册

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Technical Data  
Advance Information  
MSC8101/D  
Rev. 4, 8/2002  
Networking Digital  
Signal Processor  
(mask set 2K42A)  
CPM  
SIU  
64-bit System Bus  
Interrupt  
3 × FCC  
2 × MCC  
4 × SCC  
2 × SMC  
SPI  
MEMC  
PIT  
Controller  
UTOPIA  
Interface  
64/32-bit  
System  
Bus  
Timers  
Parallel I/O  
System Protection  
Reset Control  
Clock Control  
MII  
DMA  
Engine  
Baud Rate  
Generators  
•
•
•
SIC_EXT  
SIC  
Dual Ported  
RAM  
TDMs  
{
Interrupts  
The Motorola  
MSC8101 16-bit  
Bridge  
2 × SDMA  
Digital Signal  
MEMC  
I2C  
RISC  
64-bit Local Bus  
Processor (DSP) is the  
first member of the  
family of DSPs based  
on the StarCore™  
SC140 DSP core. The  
MSC8101 is offered in  
three core speed levels:  
250, 275, and 300 MHz.  
Other  
Peripherals  
Extended Core  
PIC  
128-bit QBus  
Q2PPC  
Bridge  
Interrupts  
EFCOP  
Address  
Register  
File  
Data ALU  
Register  
File  
Program  
Sequencer  
Boot  
ROM  
8/16-bit  
Host  
Interface  
HDI16  
Address  
ALU  
Data  
ALU  
SC140  
Core  
SRAM  
512 KB  
L1 Interface  
JTAG  
EOnCE™  
128-bit P-Bus  
64-bit XA Data Bus  
64-bit XB Data Bus  
Power  
Management  
Clock/PLL  
Figure 1. MSC8101 Block Diagram  
The Motorola MSC8101 DSP is a very versatile  
Asynchronous Transfer mode (ATM) backbones.  
device that integrates the high-performance SC140 The MSC8101 60x-compatible bus interface  
four-ALU (Arithmetic Logic Unit) DSP core along facilitates its connection to multi-master system  
with 512 KB of on-chip memory, a  
Communications Processor Module (CPM), a  
architectures. The very large on-chip memory, 512  
KB, reduces the need for off-chip program and  
64-bit bus, a very flexible System Integration Unit data memories. The MSC8101 offers 1500 DSP  
(SIU), and a 16-channel DMA engine on a single MMACS (1200 core and 300 EFCOP) or 3600  
device. With its four-ALU core, the MSC8101 can RISC MIPS performance using an internal 300  
execute up to four multiply-accumulate (MAC)  
operations in a single clock cycle. The MSC8101  
CPM is a 32-bit RISC-based communications  
MHz clock with a 1.6 V core and independent  
3.3 V input/output (I/O). MSC8101 power  
dissipation is estimated at less than 0.6 W. Figure  
protocol engine that can network to Time-Division 1 shows a block diagram of the MSC8101  
Multiplexed (TDM) highways, Ethernet, and processor.  
Note: This document contains information on a new product. Specifications and information herein are subject to change without notice.  
 
 
 
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