Datasheet > XC5VFX130T

XC5VFX130T

更新时间： 2024-01-02 11:27:21

品牌	Logo	应用领域
赛灵思 - XILINX		/
页数	文件大小	规格书
13页	314K
描述
Virtex-5 Family Overview

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中文翻译

获取价格

数据手册

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XC5VFX130T 数据手册

Virtex-5 Family Overview

Virtex-5 FPGA Logic

550 MHz Integrated Block Memory

•

On average, one to two speed grade improvement over

Virtex-4 devices

•

Up to 16.4 Mbits of integrated block memory

36-Kbit blocks with optional dual 18-Kbit mode

True dual-port RAM cells

Independent port width selection (x1 to x72)

Cascadable 32-bit variable shift registers or 64-bit

distributed memory capability

Superior routing architecture with enhanced diagonal

routing supports block-to-block connectivity with

minimal hops

−

Up to x36 total per port for true dual port operation

Up to x72 total per port for simple dual port operation

(one Read port and one Write port)

−

Memory bits plus parity/sideband memory support for

x9, x18, x36, and x72 widths

Configurations from 32K x 1 to 512 x 72

(8K x 4 to 512 x 72 for FIFO operation)

•

Up to 330,000 logic cells including:

−

Up to 207,360 internal fabric flip-flops with clock enable

(XC5VLX330)

Up to 207,360 real 6-input look-up tables (LUTs) with

greater than 13 million total LUT bits

Two outputs for dual 5-LUT mode gives enhanced

utilization

•

Multirate FIFO support logic

−

Full and Empty flag with fully programmable Almost Full

and Almost Empty flags

Logic expanding multiplexers and I/O registers

•

Synchronous FIFO support without Flag uncertainty

Optional pipeline stages for higher performance

Byte-write capability

550 MHz Clock Technology

•

Up to six Clock Management Tiles (CMTs)

Dedicated cascade routing to form 64K x 1 memory

without using FPGA routing

Integrated optional ECC for high-reliability memory

requirements

Special reduced-power design for 18 Kbit (and below)

operation

−

Each CMT contains two DCMs and one PLL—up to

eighteen total clock generators

Flexible DCM-to-PLL or PLL-to-DCM cascade

Precision clock deskew and phase shift

Flexible frequency synthesis

•

−

Multiple operating modes to ease performance trade-off

decisions

−

Improved maximum input/output frequency

Fine-grained phase shifting resolution

Input jitter filtering

Low-power operation

Wide phase shift range

550 MHz DSP48E Slices

•

25 x 18 two’s complement multiplication

Optional pipeline stages for enhanced performance

Optional 48-bit accumulator for multiply accumulate

(MACC) operation with optional accumulator cascade

to 96-bits

•

Differential clock tree structure for optimized low-jitter

clocking and precise duty cycle

•

32 global clock networks

Regional, I/O, and local clocks in addition to global

clocks

•

Integrated adder for complex-multiply or multiply-add

operation

•

Optional bitwise logical operation modes

Independent C registers per slice

SelectIO Technology

•

Up to 1,200 user I/Os

Fully cascadable in a DSP column without external

routing resources

Wide selection of I/O standards from 1.2V to 3.3V

Extremely high-performance

−

Up to 800 Mb/s HSTL and SSTL

(on all single-ended I/Os)

Up to 1.25 Gb/s LVDS (on all differential I/O pairs)

−

Works in conjunction with SelectIO technology to

simplify source-synchronous interfaces

•

True differential termination on-chip

Same edge capture at input and output I/Os

Extensive memory interface support

DS100 (v5.0) February 6, 2009

www.xilinx.com

Product Specification

1 234 5 6 7...13

中文翻译

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与XC5VFX130T相关器件

型号	品牌	获取价格	描述	数据表
XC5VFX130T-1FF1738C	XILINX	获取价格	Field Programmable Gate Array, 11200 CLBs, 1098MHz, 131072-Cell, CMOS, PBGA1738, 42.50 X 4
XC5VFX130T-1FF1738I	XILINX	获取价格	Field Programmable Gate Array, 11200 CLBs, 1098MHz, 131072-Cell, CMOS, PBGA1738, 42.50 X 4
XC5VFX130T-1FFG1738I	XILINX	获取价格	暂无描述
XC5VFX130T-1FFV1738C	XILINX	获取价格	Field Programmable Gate Array, 10240 CLBs, 13172-Cell, PBGA1738, BGA-1738
XC5VFX130T-1FFV1738I	XILINX	获取价格	Field Programmable Gate Array, 10240 CLBs, 13172-Cell, PBGA1738, BGA-1738
XC5VFX130T-2FF1738C	XILINX	获取价格	Field Programmable Gate Array, 11200 CLBs, 1265MHz, 131072-Cell, CMOS, PBGA1738, 42.50 X 4
XC5VFX130T-2FF1738I	XILINX	获取价格	Field Programmable Gate Array, 11200 CLBs, 1265MHz, 131072-Cell, CMOS, PBGA1738, 42.50 X 4
XC5VFX130T-2FFG1738I	XILINX	获取价格	Field Programmable Gate Array, 11200 CLBs, 1265MHz, 131072-Cell, CMOS, PBGA1738, 42.50 X 4
XC5VFX130T-2FFV1738C	XILINX	获取价格	Field Programmable Gate Array, 10240 CLBs, 13172-Cell, PBGA1738, BGA-1738
XC5VFX130T-3FF1738C	XILINX	获取价格	Field Programmable Gate Array, 1412MHz, 131072-Cell, CMOS, PBGA1738, 42.50 X 42.50 MM, FBG

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