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X9315WSIT1

更新时间： 2024-01-20 01:16:11
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
16页 715K
描述
Low Noise, Low Power, 32 Taps Digitally Controlled Potentiometer (XDCP™)

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中文翻译

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X9315WSIT1 技术参数

生命周期：Obsolete包装说明：PLASTIC, SOIC-8
Reach Compliance Code：unknown风险等级：5.65
Base Number Matches：1

X9315WSIT1 数据手册

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DATASHEET  
X9315  
FN8179  
Rev.2.00  
December 21, 2009  
Low Noise, Low Power, 32 Taps Digitally Controlled Potentiometer  
(XDCP™)  
The Intersil X9315 is a digitally controlled potentiometer  
(XDCP). The device consists of a resistor array, wiper  
switches, a control section, and nonvolatile memory. The  
wiper position is controlled by a 3-wire interface.  
Features  
• Solid-state potentiometer  
• 3-wire serial interface  
The potentiometer is implemented by a resistor array  
composed of 31 resistive elements and a wiper switching  
network. Between each element and at either end are tap  
points accessible to the wiper terminal. The position of the  
wiper element is controlled by the CS, U/D, and INC inputs.  
The position of the wiper can be stored in nonvolatile  
memory and then be recalled upon a subsequent power-up  
operation.  
• 32 wiper tap points  
- Wiper position stored in nonvolatile memory and  
recalled on power-up  
• 31 resistive elements  
- Temperature compensated  
- End to end resistance range ± 20%  
- Terminal voltage, 0 to V  
CC  
• Low power CMOS  
The device can be used as a three-terminal potentiometer or  
as a two-terminal variable resistor in a wide variety of  
applications including:  
- V  
CC  
= 2.7V or 5V  
- Active current, 80/400µA max.  
- Standby current, 5µA max.  
• Control  
• High reliability  
• Parameter Adjustments  
• Signal Processing  
- Endurance, 100,000 data changes per bit  
- Register data retention, 100 years  
• R  
TOTAL  
values = 10k, 50k, 100k  
• Packages  
- 8 Ld SOIC, MSOP and PDIP  
• Pb-free available (RoHS compliant)  
Block Diagram  
U/D  
INC  
CS  
5-Bit  
R /V  
31  
H
H
Up/Down  
Counter  
V
(Supply Voltage)  
CC  
30  
29  
28  
R /V  
H
H
Up/Down  
(U/D)  
5-Bit  
Nonvolatile  
Memory  
Control  
and  
One  
of  
Increment  
(INC)  
R
/V  
W
W
Memory  
Transfer  
Gates  
Resistor  
Array  
Thirty  
Device Select  
(CS)  
Two  
R /V  
Decoder  
L
L
2
Store and  
Recall  
Control  
Circuitry  
V
(Ground)  
SS  
1
0
V
V
CC  
SS  
General  
R /V  
L
L
/V  
R
W
W
Detailed  
FN8179 Rev.2.00  
December 21, 2009  
Page 1 of 16  
1234567...16

中文翻译

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