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X84256V14-2.5 PDF预览

X84256V14-2.5

更新时间: 2024-01-13 13:12:54
品牌 Logo 应用领域
XICOR 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
15页 72K
描述
UPort Saver EEPROM

X84256V14-2.5 数据手册

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Preliminary  
256K  
MPS EEPROM  
X84256  
µPort Saver EEPROM  
DESCRIPTION  
FEATURES  
• Up to 10MHz data transfer rate  
• 25ns Read Access Time  
• Direct Interface to Microprocessors and  
Microcontrollers  
—Eliminates I/O port requirements  
—No interface glue logic required  
Eliminates need for parallel to serial converters  
• Low Power CMOS  
—2.5V–5.5V and 5V ±10% Versions  
—Standby Current Less than 1µA  
—Active Current Less than 3mA  
• Byte or Page Write Capable  
—64-Byte Page Write Mode  
• Typical Nonvolatile Write Cycle Time: 2ms  
• High Reliability  
—1,000,000 Endurance Cycles  
—Guaranteed Data Retention: 100Years  
• Small Packages Options  
—8, 16-Lead SOIC Packages  
—14-Lead TSSOP Packages  
—8-Lead XBGA Packages  
The µPort Saver memories need no serial ports or spe-  
cial hardware and connect to the processor memory bus.  
Replacing bytewide data memory, the µPort Saver uses  
bytewide memory control functions, takes a fraction of  
the board space and consumes much less power.  
Replacing serial memories, the µPort Saver provides all  
the serial benefits, such as low cost, low power, low volt-  
age, and small package size while releasing I/Os for  
more important uses.  
The µPort Saver memory outputs data within 25ns of an  
active read signal. This is less than the read access time  
of most hosts and provides “no-wait-state” operation.  
This prevents bottlenecks on the bus. With rates to 10  
MHz, the µPort Saver supplies data faster than required  
by most host read cycle specifications. This eliminates  
the need for software NOPs.  
The µPort Saver memories communicate over one line  
of the data bus using a sequence of standard bus read  
and write operations. This “bit serial” interface allows the  
µPort Saver to work well in 8-bit, 16 bit, 32-bit, and 64-bit  
systems.  
A Write Protect (WP) pin prevents inadvertent writes to  
the memory.  
Xicor EEPROMs are designed and tested for applica-  
tions requiring extended endurance. Inherent data reten-  
tion is greater than 100 years.  
BLOCK DIAGRAM  
System Connection  
Internal Block Diagram  
MPS  
WP  
H.V. GENERATION  
TIMING & CONTROL  
A15  
µP  
µC  
A0  
D7  
DSP  
ASIC  
RISC  
CE  
I/O  
OE  
EEPROM  
ARRAY  
COMMAND  
DECODE  
AND  
CONTROL  
LOGIC  
X
DEC  
D0  
OE  
WE  
32K x 8  
P0/CS  
P1/CLK  
P2/DI  
Ports  
Saved  
WE  
P3/DO  
Y DECODE  
DATA REGISTER  
Xicor, Inc. 1998 Patents Pending  
4005 1 8/24/99 WW  
Characteristics subject to change without notice  
1

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