November 2006
rev 1.6
P2040C
Pin Configuration
1
8
8
1
CLKIN
MRA
SR1
VDD
2
2
7
7
SR0
P2040C
6
6
33
ModOUT
SSON#
5
5
4
4
VSS
Pin Description
Pin
Pin#
Type
Description
Name
1
2
3
4
CLKIN
MRA
SR1
I
I
External reference frequency input. Connect to externally generated reference signal.
Digital logic input used to select modulation rate. This pin has an internal pull-up resistor.
Digital logic input used to select Spreading Range. This pin has an internal pull-up resistor.
Ground to entire chip. Connect to system ground.
I
VSS
P
Digital logic input used to enable Spread Spectrum function (Active LOW). Spread Spectrum
5
SSON#
I
function enabled when LOW, disabled when HIGH. This pin has an internal pull-low resistor.
6
7
8
ModOUT
SR0
O
I
Spread spectrum Clock Output.
Digital logic input used to select Spreading Range. This pin has an internal pull-up resistor.
Power supply for the entire chip.
VDD
P
Modulation Selection (Commercial) – Table 1
Spreading Range
MRA SR1 SR0
Modulation Rate
54MHz
±1.4%
±2.0%
±1.1%
±1.8%
±1.3%
±2.2%
±1.4%
±2.1%
65MHz
±1.2%
±1.9%
±0.9%
±1.5%
±1.3%
±2.1%
±1.3%
±2.1%
81MHz
±1.0%
±1.6%
±0.5%
±1.0%
±1.3%
±2.1%
±1.4%
±2.1%
140MHz
±0.6%
±1.0%
±0.3%
±0.54%
±1.25%
±2.0%
±1.2%
±1.9%
162MHz
±0.4%
±0.8%
±0.3%
±0.4%
±1.1%
±1.8%
±0.9%
±1.4%
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
(Fin/80) * 62.49KHz
(Fin/80) * 62.49KHz
(Fin/80) * 62.49KHz
(Fin/80) * 62.49KHz
(Fin/80) * 20.83KHz
(Fin/80) * 20.83KHz
(Fin/80) * 20.83KHz
(Fin/80) * 20.83KHz
LCD Panel EMI Reduction IC
2 of 9
Notice: The information in this document is subject to change without notice.