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X2040CG-08TR

更新时间： 2024-01-16 12:34:39

品牌	Logo	应用领域
ALSC		/
页数	文件大小	规格书
9页	159K
描述
LCD Panel EMI Reduction IC

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数据手册

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X2040CG-08TR 数据手册

September 2005

rev 1.4

P2040C

LCD Panel EMI Reduction IC

Features

system wide reduction of EMI of all clock dependent

signals. The P2040C allows significant system cost

savings by reducing the number of circuit board layers and

shielding that are traditionally required to pass EMI

regulations.

FCC approved method of EMI attenuation.

Provides up to 15dB of EMI suppression

Generates a low EMI spread spectrum clock of the

input frequency

50MHz to 170MHz input frequency range

Optimized for 54MHz, 65MHz, 81MHz, 140MHz,

and 162MHz pixel clock frequencies

Internal loop filter minimizes external components

and board space

8 selectable spread ranges, up to ± 2.2%

SSON# control pin for spread spectrum enable and

disable options

2 selectable modulation rates

Low Cycle-to-cycle jitter

3.3V Operating Voltage

Ultra low power CMOS design

The P2040C uses the most efficient and optimized

modulation profile approved by the FCC and is

implemented in a proprietary all-digital method. The

P2040C modulates the output of a single PLL in order to

“spread” the bandwidth of a synthesized clock and, more

importantly, decreases the peak amplitudes of its

harmonics. This result in a significantly lower system EMI

compared to the typical narrow band signal produced by

oscillators and most frequency generators. Lowering EMI

by increasing a signal’s bandwidth is called ‘spread

spectrum clock generation’.

Supports most mobile graphic accelerator and LCD

timing controller specifications

Available in 8 pin SOIC and TSSOP Packages

Applications

Product Description

The P2040C is targeted towards digital flat panel

applications for Notebook PCs, Palm-size PCs, Office

Automation Equipments and LCD Monitors.

The P2040C is a selectable spread spectrum frequency

modulator designed specifically for digital flat panel

applications. The P2040C reduces electromagnetic

interference (EMI) at the clock source which provides

Block Diagram

VDD

SR0 SR1 MRA

SSON#

PLL

Modulation

CLKIN

Frequency

Divider

Output

Divider

Phase

Loop

Filter

VCO

Detector

Feedback

Divider

ModOUT

VSS

Alliance Semiconductor

2575 Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com

Notice: The information in this document is subject to change without notice.

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