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X1288V14IZ-2.7A PDF预览

X1288V14IZ-2.7A

更新时间: 2024-01-24 14:08:15
品牌 Logo 应用领域
瑞萨 - RENESAS 时钟光电二极管外围集成电路
页数 文件大小 规格书
27页 433K
描述
1 TIMER(S), REAL TIME CLOCK, PDSO14, ROHS COMPLIANT, PLASTIC, TSSOP-14

X1288V14IZ-2.7A 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP14,.25
针数:14Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.63Is Samacsys:N
最大时钟频率:0.032 MHz信息访问方法:I2C
中断能力:YJESD-30 代码:R-PDSO-G14
JESD-609代码:e3长度:5 mm
湿度敏感等级:1端子数量:14
计时器数量:1最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3/5 V
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Timer or RTC最大供电电压:5.5 V
最小供电电压:2.7 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL最短时间:1/100 SECOND
处于峰值回流温度下的最长时间:NOT SPECIFIED易失性:YES
宽度:4.4 mmuPs/uCs/外围集成电路类型:TIMER, REAL TIME CLOCK
Base Number Matches:1

X1288V14IZ-2.7A 数据手册

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X1288  
AC Specifications (T = -40°C to +85°C, VCC = +2.7V to +5.5V, unless otherwise specified.)  
A
Symbol  
Parameter  
Min.  
Max. Units  
fSCL  
tIN  
SCL Clock Frequency  
400  
kHz  
ns  
µs  
µs  
µs  
µs  
µs  
µs  
ns  
µs  
µs  
ns  
ns  
ns  
pF  
Pulse width Suppression Time at inputs  
SCL LOW to SDA Data Out Valid  
Time the bus must be free before a new transmission can start  
Clock LOW Time  
50(1)  
tAA  
0.9  
tBUF  
1.3  
tLOW  
tHIGH  
tSU:STA  
tHD:STA  
tSU:DAT  
tHD:DAT  
tSU:STO  
tDH  
1.3  
Clock HIGH Time  
0.6  
Start Condition Setup Time  
Start Condition Hold Time  
Data In Setup Time  
0.6  
0.6  
100  
Data In Hold Time  
0
0.6  
Stop Condition Setup Time  
Data Output Hold Time  
50  
tR  
SDA and SCL Rise Time  
20 +.1Cb(1)(2)  
20 +.1Cb(1)(2)  
300  
300  
400  
tF  
SDA and SCL Fall Time  
Cb  
Capacitive load for each bus line  
Notes: (1) This parameter is not 100% tested.  
(2) Cb = total capacitance of one bus line in pF.  
TIMING DIAGRAMS  
Bus Timing  
tF  
tHIGH  
tLOW  
tR  
SCL  
tSU:DAT  
tSU:STA  
tHD:DAT  
tSU:STO  
tHD:STA  
SDA IN  
tAA tDH  
tBUF  
SDA OUT  
Write Cycle Timing  
SCL  
8th Bit of Last Byte  
ACK  
SDA  
tWC  
Stop  
Condition  
Start  
Condition  
FN8102.3  
6
April 14, 2006  

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