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WRF1203S-3WR2 PDF预览

WRF1203S-3WR2

更新时间: 2024-02-11 03:55:58
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RSG /
页数 文件大小 规格书
7页 658K
描述
Ultra-Miniature SIP Package

WRF1203S-3WR2 技术参数

生命周期:Contact Manufacturer包装说明:,
Reach Compliance Code:unknown风险等级:5.67
模拟集成电路 - 其他类型:DC-DC REGULATED POWER SUPPLY MODULEBase Number Matches:1

WRF1203S-3WR2 数据手册

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OUTLINE DIMENSIONS,RECOMMENDED FOOTPRINT & PACKAGING  
TEST CONFIGURATIONS  
Input Reflected-Ripple Current Test Setup  
Input reflected-ripple current is measured with an inductor Lin and Capacitor Cin to simulate the source impedance.  
Oscilloscope  
Lin  
Current  
Probe  
Load  
Cin  
DC  
DC  
Lin(4.7µH)  
Cin(220µF, ESR < 1.0Ω at 100 KHz)  
DESIGN CONSIDERATIONS  
1) Requirement on output load  
To ensure this module can operate efficiently and reliably, during operation, the minimum output load could not be less than 5% of the full load,  
otherwise output ripple maybe increase dramatically. If the actual output power is very small, please connect a resistor with proper resistance at the  
output end in parallel to increase the load, suppose to use the resistance of 5% rated power, or use our companys products with a lower rated output  
power.  
2) Recommended circuit  
All the WRE_S-3WR2 & WRF_S-3WR2 series have been tested according to the following recommended test circuit before leaving the factory  
(see Figure 6).  
If you want to further decrease the input/output ripple, you can increase a capacitance-values properly or choose capacitors with low ESR.  
However, the capacitance of the output filter capacitor must be proper. If the capacitance is too big, a startup problem might arise. For every channel  
of output, provided the safe and reliable operation is ensured, the greatest capacitance of its filter capacitor must be less than the Max. Capacitive  
Load.  
General: Cin1:  
5V&12V  
24V&48V  
100μF  
10μF  
47μF  
1μF  
Cin2: 5V&12V  
24V&48V  
Lin:  
4.7μH~12μH  
Cs:  
10μF~22μF  
Cout: 100μF(Typ.)  
Lout:  
Cd:  
2.2μH~10μH  
47nF/100V  
Single output  
Dual output  
Lin  
Lin  
Lout  
2
2
1
6
8
6
Vin  
Vin  
+Vo  
0V  
+Vo  
0V  
Cin1  
Cin2  
Cout  
Cout  
Cin1 Cin2  
7
8
Cout  
Lout  
Cs  
1
-Vo  
GND  
GND  
Vc  
7
Cd  
D1 Ic  
Cd  
D1 Ic  
R
R
3
3
Vc  
(Figure 6)  
The copyright and authority for the interpretation of the products are reserved by MORNSUN  
WRE_S-3WR2 & WRF_S-3WR2 2013.07.26-A/3 Page 6 of 7  

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