Datasheet > WED3EG7266S202BD4

WED3EG7266S202BD4

更新时间： 2024-10-01 09:27:59

品牌	Logo	应用领域
WEDC		动态存储器
页数	文件大小	规格书
10页	288K
描述
DRAM,

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WED3EG7266S202BD4 数据手册

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WED3EG7266S-D4

AD4

White Electronic Designs

BD4

PRELIMINARY*

512MB-64Mx72 DDR SDRAM UNBUFFERED ECC w/PLL

FEATURES

DESCRIPTION

Double-data-rate architecture

The WED3EG7266S is a 64Mx72 Double Data Rate

SDRAM memory module based on 512Mb DDR SDRAM

components. The module consists of nine 64Mx8 DDR

SDRAMs in 66 pin TSOP packages mounted on a 200

pin FR4 substrate.

Speeds of 100 MHz, 133 MHz, and 166 MHz

Bi-directional data strobes (DQS)

Differential clock inputs (CK & CK#)

Programmable Read Latency 2,2.5 (clock)

Programmable Burst Length (2,4,8)

Programmable Burst type (sequential & interleave)

Edge aligned data output, center aligned data input

Auto and self refresh

Synchronous design allows precise cycle control with the

use of system clock. Data I/O transactions are possible

on both edges and Burst Lengths allow the same device to

be useful for a variety of high bandwidth, high performance

memory system applications.

Serial presence detect

JEDEC standard 200 pin SO-DIMM package

Power supply: 2.5V ± 0.2V

* This data sheet describes a product that is not fully qualiﬁed or characterized and is

subject to change without notice.

Package height options: AD4: 35.5 mm (1.38")

BD4: 31.75 mm (1.25”)

March, 2004

Rev. 4

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

12 3 4 5 6 7...10

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