W3EG7266S-AD4
-BD4
White Electronic Designs
PRELIMINARY*
512MB – 64Mx72 DDR SDRAM UNBUFFERED ECC w/PLL
FEATURES
DESCRIPTION
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Double-data-rate architecture
The W3EG7266S is a 64Mx72 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. The module consists of nine 64Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 200
pin FR4 substrate.
DDR200, DDR266, DDR300 and DDR400
• JEDEC design specifications
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Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible
on both edges and Burst Lengths allow the same device to
be useful for a variety of high bandwidth, high performance
memory system applications.
* This data sheet describes a product that is not fully qualified or characterized and is
subject to change without notice.
Serial presence detect
Power supply:
• VCC = VCCQ = +2.5V 0.2V (100, 133 and
166MHz)
• VCC = VCCQ = +2.6V 0.1V (200MHz)
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JEDEC standard 200 pin SO-DIMM package
• Package height options:
AD4: 35.05 mm (1.38”)
BD4: 31.75 mm (1.25”)
NOTE: Consult factory for availability of:
• Lead-Free Products
• Vendor source control options
• Industrial temperature options
OPERATING FREQUENCIES
DDR400@CL=3
DDR333@CL=2.5
166MHz
DDR266@CL=2
133MHz
DDR266@CL=2.5
133MHz
DDR200@CL=2
100MHz
Clock Speed
CL-tRCD-tRP
200MHz
3-3-3
2.5-3-3
2-2-2
2.5-3-3
2-2-2
October 2004
Rev. 7
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com