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VSP5610RSHR PDF预览

VSP5610RSHR

更新时间： 2024-02-21 23:50:27
品牌 Logo 应用领域
德州仪器 - TI 传感器
页数 文件大小 规格书
47页 792K
描述
16-Bit, 4-Channel, CCD/CMOS Sensor Analog Front-End with Timing Generator

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VSP5610RSHR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN,针数：56
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：1.52模拟集成电路 - 其他类型：ANALOG CIRCUIT
JESD-30 代码：S-PQCC-N56JESD-609代码：e4
长度：7 mm湿度敏感等级：3
信道数量：4功能数量：1
端子数量：56最高工作温度：85 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
座面最大高度：1 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：OTHER端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：NO LEAD端子节距：0.4 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7 mmBase Number Matches：1

VSP5610RSHR 数据手册

 浏览型号VSP5610RSHR的Datasheet PDF文件第2页浏览型号VSP5610RSHR的Datasheet PDF文件第3页浏览型号VSP5610RSHR的Datasheet PDF文件第4页浏览型号VSP5610RSHR的Datasheet PDF文件第5页浏览型号VSP5610RSHR的Datasheet PDF文件第6页浏览型号VSP5610RSHR的Datasheet PDF文件第7页 
VSP5610  
VSP5611  
VSP5612  
www.ti.com  
SBES021 –JUNE 2011  
16-Bit, 4-Channel, CCD/CMOS Sensor  
Analog Front-End with Timing Generator  
Check for Samples: VSP5610, VSP5611, VSP5612  
1
FEATURES  
APPLICATIONS  
23  
•
Four-Channel CCD/CMOS Signal: 2-Channel,  
3-Channel, and 4-Channel Selectable  
Power Supply: 3.3 V Only, Typ  
(Built-in LDO, 3.3 V to 1.8 V)  
•
•
•
Copiers  
Facsimile Machines  
Scanners  
•
•
Maximum Conversion Rate:  
DESCRIPTION  
–
–
–
VSP5610: 35 MSPS  
VSP5611: 50 MSPS  
VSP5612: 70 MSPS  
The  
VSP5610/11/12  
are  
high-speed,  
high-performance, 16-bit analog-to-digital-converters  
(ADCs) that have four independent sampling circuit  
channels for multi-output charge-coupled device  
•
•
•
•
16-Bit Resolution  
CDS/SH Selectable  
Maximum Input Signal Range: 2.0 V  
Analog and Digital Hybrid Gain:  
(CCD)  
and  
complementary  
metal  
oxide  
semiconductor (CMOS) line sensors. Pixel data from  
the sensor are sampled by the sample/hold (SH) or  
correlated double sampler (CDS) circuit, and are then  
converted to digital data by an ADC. Data output is  
selectable in low-voltage differential signaling (LVDS)  
or CMOS modes.  
–
Analog Gain: 0.5 V/V to 3.5 V/V in  
3/64-V/V Steps  
–
Digital Gain: 1 V/V to 2 V/V in  
1/256-V/V Steps  
The VSP5610/11/12 include a programmable gain to  
support the pixel level inflection caused by luminance.  
The integrated digital-to-analog-converter (DAC) can  
be used to adjust the offset level for the analog input  
signal. Furthermore, the timing generator (TG) is  
integrated in these devices for the control of sensor  
operation.  
•
•
Offset Correction DAC: ±250 mV, 8-Bit  
Standard LVDS/CMOS Selectable Output:  
–
LVDS:  
–
–
–
Data Channel: 2-Channel, 3-Channel  
Clock Channel: 1-Channel  
8-Bit/7-Bit Serializer Selectable  
The VSP5610/11/12 use 1.65 V to 1.95 V for the core  
voltage and 3.0 V to 3.6 V for I/Os. The core voltage  
is supplied by a built-in low-dropout regulator (LDO).  
–
CMOS: 4 Bits × 4, 8 Bits × 2  
•
Timing Generator:  
–
–
Fast Transfer Clock: Eight Signals  
Slow Transfer Clock: Six Signals  
•
•
Timing Adjustment Resolution: tMCLK/48  
Input Clamp/Input Reference Level  
Internal/External Selectable  
•
•
•
Reference DAC: 0.5 V, 1.1 V, 1.5 V, 2 V  
SPI™: Three-Wire Serial  
GPIO: Four-Port  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
SPI is a trademark of Motorola.  
All other trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2011, Texas Instruments Incorporated  
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