Datasheet > VS8061FC

VS8061FC

更新时间： 2024-02-22 20:02:38

品牌	Logo	应用领域
VITESSE		ATM 异步传输模式
页数	文件大小	规格书
20页	408K
描述
Telecom Circuit, 1-Func, GAAS, CQFP52, HEAT SINK, CERAMIC, LDCC-52

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

VS8061FC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	HQFF, QFL52,.75SQ
针数：	52	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.92
Is Samacsys：	N	JESD-30 代码：	S-CQFP-F52
JESD-609代码：	e0	长度：	19.05 mm
负电源额定电压：	-5.2 V	功能数量：	1
端子数量：	52	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	HQFF	封装等效代码：	QFL52,.75SQ
封装形状：	SQUARE	封装形式：	FLATPACK, HEAT SINK/SLUG
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	-2,-5.2 V
认证状态：	Not Qualified	座面最大高度：	3 mm
子类别：	ATM/SONET/SDH ICs	最大压摆率：	0.52 mA
表面贴装：	YES	技术：	GAAS
电信集成电路类型：	TELECOM CIRCUIT	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	FLAT
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	19.05 mm
Base Number Matches：	1

VS8061FC 数据手册

VITESSE

SEMICONDUCTOR CORPORATION

Datasheet

2.5 Gb/s 16-Bit Multiplexer/

Demultiplexer Chipset

VSC8061/VSC8062

Features

• Power Dissipation: VS8061: 2.0W(max),

• Serial Data Rate up to 2.5 Gb/s

VS8062: 1.7W(max)

• 16-bit Wide ECL 100K Compatible Parallel

Data Interface

• Standard ECL Power Supplies: V_EE= -5.2

volts, V_TT= -2.0 volts

• Differential High Speed Data Outputs

• Commercial (0^oto 70^oC) or Industrial (-40^oC

to 85^oC) Temperature Range

• Differential or Single-ended High Speed Data

and Clock Inputs

• Available in 52-pin Ceramic Leaded Chip Car-

rier Package or 52-pin Plastic Quad Flat Pack

• On-chip Phase Detector (VS8061 Multiplexer)

Functional Description

The VS8061 and VS8062 are high speed interface devices capable of data rates up to 2.5 Gb/s. These

devices are fabricated in gallium arsenide using the Vitesse H-GaAs E/D MESFET process to achieve high

speed and low power dissipation. For ease of system design using these products, both devices use industry

standard, -5.2V and -2V, power supplies, and have ECL compatible I/O for parallel data interfaces. Typical

applications include telecommunication transmission and instrumentation.

VS8061 Multiplexer

The VS8061 consists of a 16:1 multiplexer circuit, a phase detector, and a timing circuit which generates a

divide-by-16 clock from the high speed clock input. The 16:1 multiplexer accepts 16 parallel single-ended ECL

compatible inputs (D0..D15) at data rates up to 156Mb/s and bitwise serializes them into a 2.5Gb/s serial output

(DO/DON). The internal timing of the VS8061 is referenced to the negative going edge of the high speed clock

true input (CLK). This clock is divided by 16 and is provided as an output (CLK16/CLK16N). The setup and

hold time of the parallel inputs (D0..D15) are specified with respect to the falling edge of CLK16, so that

CLK16/CLK16N can be used to clock the data source of D0..D15. The on-chip phase detector monitors the

phase relationship between the internally generated divide by 16 clock and an externally supplied low speed ref-

erence clock input (DCLK/DCLKN). Phase difference between these two clock signals generates an up or down

output (U, D) for phase lock applications. The phase detector can be used as part of an external Phase Locked

Loop (PLL) to implement a clock multiplication function.

In applications where a 2.5 GHz system clock is provided, and the phase detector function is not required, it

is recommended to connect one side of the DCLK/DCLKN input to V_TTthrough a 50 ohm resistor. The U and D

output can be left open and unused.

VS8062 Demultiplexer

The VS8062 consists of a 1:16 demultiplexer and timing circuitry which generates a divide-by-16 clock

from the high speed clock input. The demultiplexer accepts a serial data stream input (DI/DIN) at up to 2.5Gb/s

and deserializes it into 16 parallel single-ended ECL compatible outputs (D0..D15) at data rates up to 156 Mb/s.

The internal timing of the VS8062 is referenced to the negative going edge of the high speed clock true input

(CLK). This clock is divided by 16 and provided as an output (CLK16/ CLK16N). The timing parameters of the

parallel data outputs (D0..D15) are specified with respect to the falling edge of CLK16, so that CLK16/

CLK16N can be used to clock the destination of D0..D15.

G52069-0, Rev. 4.1

6/22/99

VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

Page 1

12 3 4 5 6 7...20

下载PDF

与VS8061FC相关器件

型号	品牌	描述	获取价格	数据表
VS8061FI	VITESSE	Telecom Circuit, 1-Func, GAAS, CQFP52, HEAT SINK, CERAMIC, LDCC-52	获取价格
VS8061QH	VITESSE	Telecom Circuit, 1-Func, GAAS, PQFP52, PLASTIC, QFP-52	获取价格
VS8062FC	VITESSE	Telecom Circuit, 1-Func, GAAS, CQFP52, HEAT SINK, CERAMIC, LDCC-52	获取价格
VS8062FI	VITESSE	Telecom Circuit, 1-Func, GAAS, CQFP52, HEAT SINK, CERAMIC, LDCC-52	获取价格
VS8062QH	ETC	ATM/SONET Demultiplexer	获取价格
VS809-11	TE	VERTICAL LIQUID LEVEL SWITCHES	获取价格

产品中心

服务支持

精选活动

关于我们

帮助中心

VS8061FC

VS8061FC 技术参数

VS8061FC 数据手册

与VS8061FC相关器件

与VS8061FC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

VS8061FC

VS8061FC 技术参数

VS8061FC 数据手册

与VS8061FC相关器件

与VS8061FC相关文章

您还可以找

您在本页遇到什么问题？