other VFC circuits. One period (from rising edge to rising
edge) of the clock input determines the integrator reset
period.
THEORY OF OPERATION
The VFC101 voltage-to-frequency converter provides digi-
tal output pulses with an average frequency proportional to
the analog input voltage. The output is an active low pulse
of constant duration, with a repetition rate determined by the
input voltage. Falling edges of the output pulses are synchro-
nized with rising edges of the clock input.
When the negative-going integration of the input signal
crosses the comparator threshold, integration of the input
signal will continue until the reset period can start (awaiting
the necessary transitions of the clock). Output pulses are
thus made to align with rising edges of the external clock.
This causes the instantaneous output frequency to be a
subharmonic of the clock frequency. The average frequency,
however, will be an accurate analog of the input voltage.
Operation is similar to a conventional charge-balance VFC.
An input operational amplifier (Figure 1) is configured as an
integrator so that a positive input voltage causes an input
current to flow in CINT. This forces the integrator output to
ramp negatively. When the output of the integrator crosses
the reference voltage (5V), the comparator trips, activating
the clocked logic circuit. Once activated, the clocked logic
awaits a falling edge of the clock input, followed by a rising
edge. On the rising edge, switch SW1 is closed for one
complete clock cycle, causing the reset current, I1, to switch
to the integrator input. Since I1 is larger than the input
current, IIN, the output of the integrator ramps positively
during the one clock cycle reset period. The clocked logic
circuitry also generates a VFC output pulse during the reset
period.
A full-scale input causes a nominal output frequency equal
to one-half the clock frequency. The transfer function is
fOUT = (VIN/2VFS) fCLOCK
.
Input voltages greater than VFS cause the output frequency
to limit at half the clock frequency. Negative inputs cause all
output pulses to cease. The full-scale input voltage, VFS, is
determined by the input pin used—see Figure 1.
One of the useful functions made possible by the VFC101’s
multiple input resistors is shown in Figure 2. By connecting
one 10V input to the 5V VREF output, the other 10V input pin
functions as a bipolar input. A –5V to +5V input range
causes a zero to fCLOCK/2 output frequency range. Accurate
ratio matching and temperature tracking of the input resis-
tors provides improved stability of the half-scale offset.
Unlike conventional VFC circuits, the VFC101 accurately
derives its reset period from an external clock frequency.
This eliminates the critical timing capacitor required by
INPUT
Pin Number
FULL-SCALE VOLTAGE
VRS
8
10
9
10V
10V
8V
7
7(1)
5V
2.5V
NOTE: (1) Pin 8 connected to pin 5.
+VCC
fCLOCK
CINT
+VL
0.1µF
0.1µF
TTL/CMOS
0 to 10V
2
8
17
13
5
4
14
15
+VCC
Comparator
fOUT
0 to fCLOCK/2
10kΩ
10kΩ
Integrator
Clocked
Logic
Output
One-Shot
7
9
0 to 5V
0 to 8V
16kΩ
SW1
1mA
4kΩ
Digital
VIN
10
6
Ground
5V
Reference
I1
–VCC
–VCC
16
12
+VCC
18
20
11
0.1µF
Analog
Ground
–VCC
Clock
Integrator 5V
fO
FIGURE 1. Basic Voltage-to-Frequency Operations.
®
VFC101
5
5秒后页面跳转
PAM8403音频功率放大器：资料手册参数分析
LAN8720以太网收发器：资料手册参数分析
SI2301 N沟道MOSFET：资料手册参数分析
ADC0809逐次逼近寄存器型模数转换器：资料手册参数分析
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
