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USBN9604-28M PDF预览

USBN9604-28M

更新时间： 2024-02-17 03:13:15
品牌 Logo 应用领域
美国国家半导体 - NSC 外围集成电路光电二极管控制器时钟
页数 文件大小 规格书
60页 541K
描述
USBN9603/USBN9604 Universal Serial Bus Full Speed Node Controller with Enhanced DMA Support

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中文翻译

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USBN9604-28M 技术参数

是否无铅： 不含铅生命周期：Active
零件包装代码：SOIC包装说明：SO-28
针数：28Reach Compliance Code：unknown
风险等级：5.66地址总线宽度：8
最大时钟频率：24 MHz外部数据总线宽度：8
JESD-30 代码：R-PDSO-G28JESD-609代码：e3
长度：17.9 mm湿度敏感等级：3
端子数量：28最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
认证状态：COMMERCIAL座面最大高度：2.65 mm
最大供电电压：5.5 V最小供电电压：3 V
标称供电电压：5 V表面贴装：YES
温度等级：COMMERCIAL端子面层：TIN
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：7.5 mmuPs/uCs/外围集成电路类型：BUS CONTROLLER, UNIVERSAL SERIAL BUS
Base Number Matches：1

USBN9604-28M 数据手册

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- May 1998  
June 2003  
Revision 1.3  
USBN9603/USBN9604 Universal Serial Bus  
Full Speed Node Controller with Enhanced DMA Support  
General Description  
Outstanding Features  
●
The USBN9603/4 are integrated, USB Node controllers.  
Other than the reset mechanism for the clock generation cir-  
cuit, these two devices are identical. All references to “the  
device” in this document refer to both devices, unless other-  
wise noted.  
Low EMI, low standby current, 24 MHz oscillator  
●
Advanced DMA mechanism  
●
Fully static HALT mode with asynchronous wake-up  
for bus powered operation  
The device provides enhanced DMA support with many au-  
tomatic data handling features. It is compatible with USB  
specification versions 1.0 and 1.1, and is an advanced ver-  
sion of the USBN9602.  
●
5V or 3.3V operation  
●
Improved input range 3.3V signal voltage regulator  
●
All unidirectional FIFOs are 64 bytes  
The device integrates the required USB transceiver with a  
3.3V regulator, a Serial Interface Engine (SIE), USB end-  
point (EP) FIFOs, a versatile 8-bit parallel interface, a clock  
generator and a MICROWIRE/PLUS™ interface. Seven  
endpoint pipes are supported: one for the mandatory con-  
trol endpoint and six to support interrupt, bulk and isochro-  
nous endpoints. Each endpoint pipe has a dedicated FIFO,  
8 bytes for the control endpoint and 64 bytes for the other  
endpoints. The 8-bit parallel interface supports multiplexed  
and non-multiplexed style CPU address/data buses. A pro-  
grammable interrupt output scheme allows device configu-  
ration for different interrupt signaling requirements.  
●
Power-up reset and startup delay counter simplify sys-  
tem design  
●
Simple programming model controlled by external controller  
●
Available in two packages  
— USBN9603/4SLB: small footprint for new designs  
and portable applications  
— USBN9603/4-28M: standard package, pin-to-pin  
compatible with USBN9602-28M  
Block Diagram  
A0/ALE D7-0/AD7-0  
INTR MODE1-0  
CS RD WR  
RESET  
VCC  
GND  
Microcontroller Interface  
XIN  
24 MHz  
Oscillator  
XOUT  
Endpoint/Control FIFOs  
Clock  
Generator  
CLKOUT  
Serial Interface Engine (SIE)  
Clock  
Recovery  
Media Access Controller (MAC)  
USB Event  
Detect  
Physical Layer Interface (PHY)  
V3.3  
Transceiver  
VReg  
AGND  
Upstream Port  
D+  
D-  
National Semiconductor is a registered trademark of National Semiconductor Corporation.  
All other brand or product names are trademarks or registered trademarks of their respective holders.  
www.national.com  
© National Semiconductor Corporation, 2003  
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