µPSD3200 FAMILY
SUMMARY DESCRIPTION
■ Dual bank Flash memories
– One 16-bit PWM unit
– Concurrent operation, read from memory one
while erasing and writing the other. In-Appli-
cation Programming(IAP) for remote updates
■ Standalone Display Data Channel (DDC)
– For use in monitor, projector, and TV applica-
tions
– Large 128 KByte or 256 KByte main Flash
memory for application code, operating sys-
tems, or bit maps for graphic user interfaces
– Compliant with VESA standards DDC1 and
DDC2B
– Eliminate external DDC PROM
– Large 32 KByte secondary Flash memory di-
vided in small sectors. Eliminate external EE-
PROM with software EEPROM emulation
■ Six I/O ports with up to 50 I/O pins
2
– Multifunction I/O: GPIO, DDC, I C, PWM,
PLD I/O, supervisor, and JTAG
– Secondary Flash memory is large enough for
sophisticated communication protocol (USB)
during IAP while continuing critical system
tasks
– Eliminates need for external latches and logic
■ 3000 gate PLD with 16 macrocells
– Create glue logic, state machines, delays,
etc.
■ Large SRAM with battery back-up option
– Eliminate external PALs, PLDs, and 74HCxx
– Simple PSDsoft Express software ...Free
■ Supervisor functions
– 8 KByte SRAM for RTOS, high-level languag-
es, communication buffers, and stacks
■ Programmable Decode PLD for flexibleaddress
mapping of all memories
– Generates reset upon low voltage or watch-
dog time-out. Eliminate external supervisor
device
– Place individual Flash and SRAM sectors on
any address boundary
– Built-in page register breaks restrictive 8032
limit of 64 KByte address space
– Reset In pin
■ In-System Programming (ISP) via JTAG
– Special register swaps Flash memory seg-
ments between 8032 “program” space and
“data” space for efficient In-Application Pro-
gramming
– Program entire chip in 10 - 25 seconds with
no involvement of 8032
– Allows efficient manufacturing, easy product
testing, and Just-In-Time inventory
■ High-speed clock standard 8032 core (12-cycle)
– Eliminate sockets and pre-programmed parts
– Program with FlashLINKTM cable and any PC
■ Content Security
– 40 MHz operation at 5 V, 24 MHz at 3.3 V
– Two UARTs with independent baud rate,
three 16-bit Timer/Counters and two External
Interrupts
– Programmable Security Bit blocks access of
device programmers and readers
■ USB Interface (µPSD3234A-40U6 only)
■ Zero-Power Technology
– Supports USB 1.1 Slow Mode (1.5 Mbit/s)
– Memories and PLD automatically reach
standby current between input changes
– Control endpoint 0 and interrupt endpoints 1
and 2
■ Packages
2
■ I C interface for peripheral connections
– 52-pin TQFP
– Capable of master or slave operation
■ Five Pulse Width Modulator (PWM) channels
– Four 8-bit PWM units
– 80-pin TQFP: allows access to 8032 address/
data/control signals for connecting to external
peripherals
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