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UPD44325092F5-E40-EQ2 PDF预览

UPD44325092F5-E40-EQ2

更新时间： 2024-02-22 14:39:42
品牌 Logo 应用领域
日电电子 - NEC 静态存储器
页数 文件大小 规格书
32页 348K
描述
36M-BIT QDRII SRAM 2-WORD BURST OPERATION

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UPD44325092F5-E40-EQ2 技术参数

是否Rohs认证： 符合生命周期：Transferred
包装说明：13 X 15 MM, LEAD FREE, PLASTIC, BGA-165Reach Compliance Code：compliant
风险等级：5.78最长访问时间：0.45 ns
JESD-30 代码：R-PBGA-B165JESD-609代码：e1
长度：15 mm内存密度：37748736 bit
内存集成电路类型：QDR SRAM内存宽度：9
功能数量：1端子数量：165
字数：4194304 words字数代码：4000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：4MX9
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified座面最大高度：1.51 mm
最大供电电压 (Vsup)：1.9 V最小供电电压 (Vsup)：1.7 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：TIN SILVER COPPER端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：13 mm
Base Number Matches：1

UPD44325092F5-E40-EQ2 数据手册

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PRELIMINARY DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD44325082, 44325092, 44325182, 44325362  
36M-BIT QDRTMII SRAM  
2-WORD BURST OPERATION  
Description  
The µPD44325082 is a 4,194,304-word by 8-bit, the µPD44325092 is a 4,194,304-word by 9-bit, the µPD44325182 is a  
2,097,152-word by 18-bit and the µPD44325362 is a 1,048,576-word by 36-bit synchronous quad data rate static RAM  
fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.  
The µPD44325082, µPD44325092, µPD44325182 and µPD44325362 integrate unique synchronous peripheral  
circuitry and a burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive  
edge of K and /K.  
These products are suitable for application which require synchronous operation, high speed, low voltage, high density  
and wide bit configuration.  
These products are packaged in 165-pin PLASTIC FBGA.  
Features  
• 1.8 ± 0.1 V power supply and HSTL I/O  
• DLL circuitry for wide output data valid window and future frequency scaling  
• Separate independent read and write data ports with concurrent transactions  
• 100% bus utilization DDR READ and WRITE operation  
• Two-tick burst for low DDR transaction size  
• Two input clocks (K and /K) for precise DDR timing at clock rising edges only  
• Two output clocks (C and /C) for precise flight time and clock skew matching-clock  
and data delivered together to receiving device  
• Internally self-timed write control  
• Clock-stop capability with µs restart  
• User programmable impedance output  
• Fast clock cycle time : 4.0 ns (250 MHz), 5.0 ns (200 MHz)  
• Simple control logic for easy depth expansion  
• JTAG boundary scan  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
Document No. M16783EJ1V0DS00 (1st edition)  
Date Published October 2004 NS CP(K)  
Printed in Japan  
The mark  
shows major revised points.  
2003  
1234567...32

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与UPD44325092F5-E40-EQ2相关器件

型号 品牌 描述 获取价格 数据表
UPD44325092F5-E40Y-EQ2 NEC QDR SRAM, 4MX9, 0.45ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, BGA-165

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UPD44325092F5-E40Y-EQ2-A NEC QDR SRAM, 4MX9, 0.45ns, CMOS, PBGA165, 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165

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UPD44325092F5-E50-EQ2 NEC 36M-BIT QDRII SRAM 2-WORD BURST OPERATION

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UPD44325092F5-E50-EQ2-A NEC QDR SRAM, 4MX9, 0.45ns, CMOS, PBGA165, 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165

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UPD44325094BF5-E33-FQ1 RENESAS 4MX9 QDR SRAM, 0.45ns, PBGA165, 15 X 17 MM, PLASTIC, BGA-165

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UPD44325094BF5-E33Y-FQ1 RENESAS 4MX9 QDR SRAM, 0.45ns, PBGA165, 15 X 17 MM, PLASTIC, BGA-165

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