µPD3728DZ
ABSOLUTE MAXIMUM RATINGS (TA = +25°C)
Parameter
Symbol
Ratings
−0.3 to +15
−0.3 to +8
−0.3 to +8
−0.3 to +8
−0.3 to +8
−25 to +60
−40 to +100
Unit
V
Output drain voltage
VOD
Shift register clock voltage
Reset gate clock voltage
Vφ 1, Vφ 1L, Vφ 10, Vφ 2, Vφ 20
V
Vφ RB
V
Reset feed-through level clamp clock voltage
Transfer gate clock voltage
Operating ambient temperatureNote
Storage temperature
Vφ CLB
V
Vφ TG1 to Vφ TG3
V
TA
°C
°C
Tstg
Note Use at the condition without dew condensation.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (TA = +25°C)
Parameter
Output drain voltage
Symbol
Min.
11.4
4.5
Typ.
12.0
5.0
0
Max.
12.6
5.5
Unit
V
VOD
Shift register clock high level
Shift register clock low level
Reset gate clock high level
Reset gate clock low level
Vφ 1H, Vφ 1LH, Vφ 10H, Vφ 2H, Vφ 20H
V
Vφ 1L, Vφ 1LL, Vφ 10L, Vφ 2L, Vφ 20L
−0.3
4.5
+0.5
5.5
V
Vφ RBH
Vφ RBL
5.0
0
V
−0.3
4.5
+0.5
5.5
V
Reset feed-through level clamp clock high level Vφ CLBH
5.0
0
V
Reset feed-through level clamp clock low level
Transfer gate clock high level
Vφ CLBL
−0.3
4.5
+0.5
V
Note
Vφ 1H
Note
Vφ 1H
Vφ TG1H to Vφ TG3H
V
(Vφ 10H)
(Vφ 10H)
+0.5
40
Transfer gate clock low level
Data rate
Vφ TG1L to Vφ TG3L
2fφ RB
−0.3
0
2
V
−
MHz
Note When Transfer gate clock high level (Vφ TG1H to Vφ TG3H) is higher than Shift register clock high level (Vφ 1H
(Vφ 10H)), Image lag can increase.
Remark Pin 9 ( φ10) and pin 28 ( φ20) should be open to decrease the influence of input clock noise to output
signal waveform, in case of operating at low or middle speed range; data rate under 24 MHz or so.
4
Data Sheet S15417EJ2V0DS