5秒后页面跳转
UPD3719 PDF预览

UPD3719

更新时间: 2024-02-24 19:51:14
品牌 Logo 应用领域
日电电子 - NEC 传感器图像传感器
页数 文件大小 规格书
20页 148K
描述
10600 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR

UPD3719 技术参数

是否Rohs认证:不符合生命周期:Active
Reach Compliance Code:unknown风险等级:5.81
Is Samacsys:N水平像素:10600
JESD-609代码:e0安装特点:THROUGH HOLE MOUNT
最低工作温度:-25 °C像素大小:7X7 µm
电源:15 V子类别:CCD Image Sensors
表面贴装:NO端子面层:Tin/Lead (Sn/Pb)
垂直像素:3Base Number Matches:1

UPD3719 数据手册

 浏览型号UPD3719的Datasheet PDF文件第2页浏览型号UPD3719的Datasheet PDF文件第3页浏览型号UPD3719的Datasheet PDF文件第4页浏览型号UPD3719的Datasheet PDF文件第6页浏览型号UPD3719的Datasheet PDF文件第7页浏览型号UPD3719的Datasheet PDF文件第8页 
µPD3719  
ABSOLUTE MAXIMUM RATINGS (TA = +25 °C)  
Parameter  
Output drain voltage  
Symbol  
Ratings  
–0.3 to +16  
–0.3 to +16  
–0.3 to +8  
–0.3 to +8  
–0.3 to +8  
–0.3 to +8  
–25 to +60  
–40 to +100  
Unit  
V
VOD  
Reset drain voltage  
VRD  
V
Shift register clock voltage  
Reset gate clock voltage  
Vφ1, Vφ2  
VφRB  
VφCLB  
VφTG  
TA  
V
V
Reset feed-through level clamp clock voltage  
Transfer gate clock voltage  
Operating ambient temperature  
Storage temperature  
V
V
°C  
°C  
Tstg  
Caution  
Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;  
exceeding the ratings could cause permanent damage. The parameters apply independently.  
RECOMMENDED OPERATING CONDITIONS (TA = +25 °C)  
Parameter  
Output drain voltage  
Symbol  
MIN.  
14.0  
14.0  
4.5  
TYP.  
15.0  
VOD  
5.0  
0
MAX.  
16.0  
VOD  
Unit  
V
VOD  
Reset drain voltage  
VRD  
V
Shift register clock high level  
Shift register clock low level  
Reset gate clock high level  
Reset gate clock low level  
Reset feed-through level clamp clock high level  
Reset feed-through level clamp clock low level  
Transfer gate clock high level  
Transfer gate clock low level  
Data rate  
Vφ1H, Vφ2H  
Vφ1L, Vφ2L  
VφRBH  
VφRBL  
5.5  
V
–0.3  
4.5  
+0.5  
5.5  
V
5.0  
0
V
–0.3  
4.5  
+0.5  
5.5  
V
VφCLBH  
VφCLBL  
VφTGH  
VφTGL  
5.0  
V
–0.3  
4.5  
0
+0.5  
V
Vφ1HNote  
Vφ1HNote  
V
–0.3  
0
1
+0.3  
2
V
fφRB  
MHz  
Note When Transfer gate clock high level (VφTGH) is higher than Shift register clock high level (Vφ1H), Image lag  
can increase.  
5

与UPD3719相关器件

型号 品牌 描述 获取价格 数据表
UPD3719D NEC 10600 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR

获取价格

UPD372 ETC

获取价格

UPD3720A NEC 2700 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR

获取价格

UPD3720ACY NEC 2700 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR

获取价格

UPD3725A NEC 5000-BIT x 3 CCD COLOR LINEAR IMAGE SENSOR

获取价格

UPD3725AD NEC 5000-BIT x 3 CCD COLOR LINEAR IMAGE SENSOR

获取价格