UC3525A

更新时间： 2024-02-25 17:36:37

品牌	Logo	应用领域
德州仪器 - TI		脉冲
页数	文件大小	规格书
9页	440K
描述
Regulating Pulse Width Modulators

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技术参数
数据手册

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UC3525A 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QLCC	包装说明：	QCCJ, LDCC20,.4SQ
针数：	20	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.68	模拟集成电路 - 其他类型：	SWITCHING CONTROLLER
控制模式：	VOLTAGE-MODE	控制技术：	PULSE WIDTH MODULATION
最大输入电压：	35 V	最小输入电压：	8 V
标称输入电压：	20 V	JESD-30 代码：	S-PQCC-J20
长度：	8.965 mm	功能数量：	1
端子数量：	20	最高工作温度：	70 °C
最低工作温度：		最大输出电流：	0.5 A
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装等效代码：	LDCC20,.4SQ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	座面最大高度：	4.57 mm
子类别：	Switching Regulator or Controllers	表面贴装：	YES
切换器配置：	PUSH-PULL	最大切换频率：	500 kHz
技术：	BIPOLAR	温度等级：	COMMERCIAL
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	8.965 mm	Base Number Matches：	1

UC3525A 数据手册

UC1525A/27A

UC2525A/27A

UC3525A/27A

Regulating Pulse Width Modulators

FEATURES

DESCRIPTION

• 8 to 35V Operation

The UC1525A/1527A series of pulse width modulator integrated circuits are de-

signed to offer improved performance and lowered external parts count when

used in designing all types of switching power supplies. The on-chip +5.1V ref-

erence is trimmed to ±1% and the input common-mode range of the error ampli-

fier includes the reference voltage, eliminating external resistors. A sync input to

the oscillator allows multiple units to be slaved or a single unit to be synchro-

nized to an external system clock. A single resistor between the C_Tand the dis-

charge terminals provides a wide range of dead-time adjustment. These

devices also feature built-in soft-start circuitry with only an external timing ca-

pacitor required. A shutdown terminal controls both the soft-start circuitry and

the output stages, providing instantaneous turn off through the PWM latch with

pulsed shutdown, as well as soft-start recycle with longer shutdown commands.

These functions are also controlled by an undervoltage lockout which keeps the

outputs off and the soft-start capacitor discharged for sub-normal input volt-

ages. This lockout circuitry includes approximately 500mV of hysteresis for jit-

ter-free operation. Another feature of these PWM circuits is a latch following the

comparator. Once a PWM pulse has been terminated for any reason, the out-

puts will remain off for the duration of the period. The latch is reset with each

clock pulse. The output stages are totem-pole designs capable of sourcing or

sinking in excess of 200mA. The UC1525A output stage features NOR logic,

giving a LOW output for an OFF state. The UC1527A utilizes OR logic which

results in a HIGH output level when OFF.

• 5.1V Reference Trimmed to ±1%

• 100Hz to 500kHz Oscillator Range

• Separate Oscillator Sync Terminal

• Adjustable Deadtime Control

• Internal Soft-Start

• Pulse-by-Pulse Shutdown

• Input Undervoltage Lockout with

Hysteresis

• Latching PWM to Prevent Multiple

Pulses

• Dual Source/Sink Output Drivers

BLOCK DIAGRAM

OSC

OUT

VREF

NOR

UVLO

Lockout

Reference

Regulator

+VIN 15

OUTPUT A

GROUND 12

To internal

circuitry

SYNC

Flip

Flop

NOR

OSC

OUTPUT B

DISCHARGE

UC1525A Output Stage

COMP

COMPENSATION

INV INPUT

PWM

La tch

Error

Amp

V_REF

50 µA

OUTPUT A

NI INPUT

SOFTSTART

3 kΩ

SHUTDOWN 10

OUTPUT B

5 kΩ

UC1527A Output Stage

SLUS191B - February 1997 - Revised June 2005

12 3 4 5 6 7...9

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