UNISONIC TECHNOLOGIES CO., LTD
U74LVC1G74
CMOS IC
SINGLE
POSITIVE-EDGE-TRIGGERED
D-TYPE FLIP-FLOP WITH
CLEAR AND PRESET
DESCRIPTION
SOP-8
This single positive-edge-triggered D-type flip-flop is designed for
1.65V to 5.5V VCC operation.
A low level at the preset(
) or clear (
) input sets or
CLR
PRE
resets the outputs, regardless of the levels of the other inputs .when
and are inactive(high),data at the data (D) input meeting
PRE
CLR
the setup time requirements is transferred to the outputs on the
positive-going edge of the clock pulse. Clock triggering occurs at a
voltage level and is not related directly to the rise time of the clock
pulse. Following the hold-time interval, data at the D input can be
changed without affecting the levels at the outputs.
The device is fully specified for partial-power-down applications
using Ioff. The Ioff circuitry disables the outputs, preventing damaging
current backflow through the device when it is powered down.
FEATURES
* Supports 5-V VCC operation
* Inputs accept voltages to 5.5V
* Max tpd of 5.9ns at 3.3V
* Typical VOLP<0.8V at VCC=3.3V, TA=25°C
* Typical VOHV>2V at VCC=3.3V, TA=25°C
* Low Power Consumption, ICC=10μA (Max.)
* Ioff Supports Live Insertion, Partial Power Down Mode, and Back
Drive Protection
ORDERING INFORMATION
Ordering Number
Lead Free
Package
Packing
Halogen Free
U74LVC1G74L-S08-T
U74LVC1G74L-S08-R
U74LVC1G74G-S08-T
U74LVC1G74G-S08-R
SOP-8
SOP-8
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