Datasheet > TVP3030-250MEP

TVP3030-250MEP

更新时间： 2024-02-07 15:07:21

品牌	Logo	应用领域
德州仪器 - TI		时钟外围集成电路
页数	文件大小	规格书
107页	486K
描述
1600X1280 PIXELS PALETTE-DAC DSPL CTLR, MQFP208, MQFP-208

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TVP3030-250MEP 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	FQFP,	针数：	208
Reach Compliance Code：	not_compliant	ECCN代码：	3A001.A.3
HTS代码：	8542.31.00.01	Factory Lead Time：	1 week
风险等级：	5.65	地址总线宽度：	4
最大时钟频率：	140 MHz	显示配置：	1600 X 1280 PIXELS
外部数据总线宽度：	8	JESD-30 代码：	S-MQFP-G208
长度：	27.64 mm	端子数量：	208
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	METAL	封装代码：	FQFP
封装形状：	SQUARE	封装形式：	FLATPACK, FINE PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
座面最大高度：	4.2 mm	最大供电电压：	5.25 V
最小供电电压：	4.75 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	27.64 mm
uPs/uCs/外围集成电路类型：	DISPLAY CONTROLLER, PALETTE DAC	Base Number Matches：	1

TVP3030-250MEP 数据手册

1 Introduction

The TVP3030 is an advanced video interface palette (VIP) from Texas Instruments implemented in EPIC

0.8-micron CMOS process. The TVP3030 is a 128-bit VIP that provides virtually all features of the 64-bit

TVP3026. The TVP3030 doubles the pixel bus bandwidth, enabling 24-bit/pixel displays at resolutions up

to 1600 × 1280 at a 76-Hz refresh rate. Also, 24-bit/pixel graphics at 1280 × 1024 resolution may be

implemented at higher refresh rates with or without the use of pixel packing.

With the wider pixel bus comes additional 24-bit/pixel multiplexing modes: 4:1 (128-bit bus width for overlay

andRGB)and5:1(120-bitbuswidthforRGB). Thebyterouterfunctionallowspseudo-colorormonochrome

image data to be taken from the red, green, or blue color channels. This enables high performance

24-bit/pixel architectures organized as red, green, and blue memory banks to provide 8-bit/pixel modes as

well.

The TVP3030 extends the packed-24 modes to include 16:3 (pixels:load clocks) using a 128-bit pixel bus

width. This enables, for example, 24-bit/pixel graphics at 220 MHz pixel rate with only a 40 MHz VRAM serial

output. With the 8:3 packed-24 mode (64-bit pixel bus width), a 24-bit/pixel display with 1280 x 1024

resolution may be packed into 4 megabytes of VRAM. A PLL-generated, 50 % duty cycle reference clock

is output in the packed-24 modes, maximizing VRAM cycle time.

The TVP3030 supports all of the pixel formats of the TVP3026 VIP. Data can be split into 4 or 8 bit planes

for pseudo-color mode or split into 12-, 16- or 24-bit true-color and direct-color modes. For the 24-bit direct

color modes, an 8-bit overlay plane is available. The 16-bit direct- and true-color modes can be configured

to IBM XGA (5, 6, 5), TARGA (5, 5, 5, 1), or (6, 6, 4) as another existing format. An additional 12-bit mode

(4, 4, 4, 4) is supported with 4 bits for each color and overlay. All color modes support selection of little or

big endian data format for the pixel bus. Additionally, the device is also software compatible with the

IMSG176/8 and Bt476/8 color palettes.

Two fully programmable PLLs for pixel clock and memory clock functions are provided for dramatic

improvements in graphics system cost and integration. A third loop clock PLL is incorporated making pixel

data latch timing much simpler than with other existing color palettes. In addition, an external digital clock

input is provided for VGA modes. The reference clock output is driven by the loop clock PLL and provides

a timing reference to the graphics accelerator. The shift clock output may be used directly as the VRAM shift

clock.

Like the TVP3026, the TVP3030 also integrates a complete, IBM XGA-compatible hardware cursor on chip,

making significant graphics performance enhancements possible. Additionally, color-keyed switching is

provided, giving the user an efficient means of combining graphic overlays and direct-color images

on-screen.

The TVP3030 has three 256-by-8 color lookup tables with triple 8-bit video digital-to-analog converters

(DACs) capable of directly driving a doubly terminated 75-Ω line. The lookup tables are designed with a

dual-ported RAM architecture that enables ultra-high speed operation.

The device features a separate VGA bus which supports the integrated VGA modes in graphics accelerator

applications, allowing efficient support for VGA graphics and text modes. The separate bus is also useful

for accepting data from the feature connector of most VGA supported personal computers, without the need

for external data multiplexing.

EPIC is a trademark of Texas Instruments Incorporated.

XGA is a registered trademark of IBM.

TARGA is a registered trademark of Truevision Incorporated.

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TVP3033-250	TI	Video Interface Palette	获取价格

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