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TVP3026-175APCE PDF预览

TVP3026-175APCE

更新时间: 2024-02-10 20:24:51
品牌 Logo 应用领域
德州仪器 - TI 显示控制器微控制器和处理器外围集成电路时钟
页数 文件大小 规格书
107页 505K
描述
Video Interface Palette

TVP3026-175APCE 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Contact Manufacturer零件包装代码:QFP
包装说明:QFP,针数:160
Reach Compliance Code:unknown风险等级:5.61
地址总线宽度:4最大时钟频率:14.31818 MHz
显示配置:1280 X 1024 PIXELS外部数据总线宽度:8
JESD-30 代码:S-PQFP-G160JESD-609代码:e0
长度:28 mm端子数量:160
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装形状:SQUARE封装形式:FLATPACK
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:4.1 mm最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:28 mmuPs/uCs/外围集成电路类型:DISPLAY CONTROLLER, PALETTE DAC
Base Number Matches:1

TVP3026-175APCE 数据手册

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1 Introduction  
The TVP3026 is an advanced video interface palette (VIP) from Texas Instruments implemented in EPIC  
0.2-micron CMOS process. The TVP3026 is a 64-bit VIP that supports packed-24 modes enabling 24-bit  
true color and high resolution at the same time without excessive amounts of frame buffer memory. For  
example, a 24-bit true color display with 1280 x 1024 resolution may be packed into 4M of VRAM. A  
PLL-generated, 50 % duty cycle reference clock is output in the packed-24 modes, maximizing VRAM cycle  
time and the screen refresh rate.  
The TVP3026 supports all of the pixel formats of the TVP3020 VIP. Data can be split into 4 or 8 bit planes  
for pseudo-color mode or split into 12-, 16- or 24-bit true-color and direct-color modes. For the 24-bit direct  
color modes, an 8-bit overlay plane is available. The 16-bit direct- and true-color modes can be configured  
to IBM XGA (5, 6, 5), TARGA (1, 5, 5, 5), or 16-bit/pixel (6, 6, 4) configuration as another existing format.  
An additional 12-bit mode with 4-bit overlay (4, 4, 4, 4) is supported with 4 bits for each color and overlay.  
All color modes support selection of little or big endian data format for the pixel bus. Additionally, the device  
is also software compatible with the INMOS IMSG176/8 and Brooktree Bt476/8 color palettes.  
Two fully programmable phase-locked loops (PLLs) for pixel clock and memory clock functions are  
provided, as well as a simple frequency doubler for dramatic improvements in graphics system cost and  
integration.AthirdloopclockPLLisincorporatedmakingpixeldatalatchtimingmuchsimplerthanwithother  
existing color palettes. In addition, four digital clock inputs (2 TTL- and 2 ECL/TTL-compatible) may be  
utilized and are software selectable. The video clock provides a software selected divide ratio of the chosen  
pixel clock. The shift clock output may be used directly as the VRAM shift clock. The reference clock output  
is driven by the loop clock PLL and provides a timing reference to the graphics accelerator.  
Like the TVP3020, the TVP3026 also integrates a complete IBM XGA-compatible hardware cursor on chip,  
making significant graphics performance enhancements possible. Additionally, hardware port select and  
color-keyed switching functions are provided, giving the user several efficient means of producing graphical  
overlays on direct-color backgrounds.  
The TVP3026 has three 256-by-8 color lookup tables with triple 8-bit video digital-to-analog converters  
(DACs) capable of directly driving a doubly terminated 75-line. The lookup tables are designed with a  
dual-ported RAM architecture that enables ultra-high speed operation. Sync generation is incorporated on  
the green output channel. Horizontal sync (HSYNC) and vertical sync (VSYNC) are pipeline delayed  
through the device and optionally inverted to indicate screen resolution to the monitor. A palette-page  
register is available to select from multiple color maps in RAM when 4 bit planes are used. This allows the  
screen colors to be changed with only one microprocessor write cycle.  
The device features a separate VGA bus which supports the integrated VGA modes in graphics accelerator  
applications, allowing efficient support for VGA graphics and text modes. The separate bus also is useful  
for accepting data from the feature connector of most VGA-supported personal computers, without the need  
for external data multiplexing.  
The TVP3026 is highly system integrated. It can be connected to the serial port of VRAM devices without  
external buffer logic and connected to many graphics engines directly. It also supports the split shift-register  
transfer function, which is common to many industry standard VRAM devices.  
The system-integration concept is even carried further to manufacturing test and field diagnosis. To support  
these, several highly integrated test functions have been designed to enable simplified testing of the palette  
and the entire graphics system.  
EPIC is a trademark of Texas Instruments Incorporated.  
XGA is a registered trademark of International Business Machines Corporation  
TARGA is a registered trademark of Truevision Incorporated.  
Brooktree is a trademark of Brooktree Corporation.  
INMOS is a trademark of INMOS International Limited.  
1–1  

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