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TSB43AA82PGEG4 PDF预览

TSB43AA82PGEG4

更新时间： 2024-09-28 15:55:07
品牌 Logo 应用领域
德州仪器 - TI PC
页数 文件大小 规格书
5页 103K
描述
2 Port High Performance Integrated Phy and Link Layer Chip for PC Peripherals 144-LQFP 0 to 70

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中文翻译

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TSB43AA82PGEG4 技术参数

是否无铅：不含铅生命周期：Obsolete
包装说明：,Reach Compliance Code：unknown
风险等级：5.03Is Samacsys：N
Base Number Matches：1

TSB43AA82PGEG4 数据手册

 浏览型号TSB43AA82PGEG4的Datasheet PDF文件第2页浏览型号TSB43AA82PGEG4的Datasheet PDF文件第3页浏览型号TSB43AA82PGEG4的Datasheet PDF文件第4页浏览型号TSB43AA82PGEG4的Datasheet PDF文件第5页 
TSB43AA82  
TSB43AA82I  
www.ti.com  
SLLA204–JUNE 2006  
(iShynx II) 1394 Integrated PHY and Link-Layer Controller  
for SBP-2 Products and DPP Products  
FEATURES  
•
Data Transfers:  
•
•
•
IEEE 1394a-2000 Compliant  
– Auto Address Increment of Direct/Indirect  
Addressing on Data Transfer (Packetizer)  
Single 3.3-V Supply  
– Automated Header Insert/Strip for DMA  
Data Transfers  
Internal 1.8-V Circuit to Reduce Power  
Consumption  
– 8-/16-Bit Asynchronous and Synchronous  
DMA I/F With Handshake and Burst Mode  
•
Integrated 400-Mbps Two-Port Physical Layer  
(PHY)  
– Supports ATAPI (Ultra-DMA) Mode and  
SCSI Mode  
•
•
Internal Voltage Regulator  
IEEE 1394 Related Functions:  
– 8-/16-Bit Data/Address Multiplex  
Microcontroller and 8-/16-Bit Separated  
Data/Address Bus  
– Automated Read Response for ConfigROM  
Register Access  
– Automated Single Retry Protocol and Split  
Transaction Control  
– Three FIFO Configurations That Support  
High Performance for the DMA and for  
Command Exchanges  
•
SBP-2 Related Functions:  
– Supports Four Initiators by Automated  
Transactions and More Can Be Supported  
Through Firmware.  
• Asynchronous Command FIFO: 1512  
Bytes  
• Config ROM/LOG FIFO: 504 Bytes  
• DMA FIFO: 4728 Bytes  
– Automated Management ORB Fetching  
– Automated Linked Command ORB Fetching  
– Automated PageTable Fetching  
•
Multiple Package Options:  
– PGE Dual 1394 Port Package, 144-Terminal  
Plastic Quad Flatpack  
– Automated Status Block Transmit  
•
Ability to Support Direct Print Protocol (DPP)  
Mode  
– GGW Commercial Dual 1394 Port Package,  
176-Terminal BGA  
– GGW Industrial Dual 1394 Port Package  
(TSB43AA82I), 176-Terminal BGA With  
Operational Range From –40°C to 85°C  
DESCRIPTION  
The TSB43AA82 is a high performance 1394 integrated PHY and link layer controller. It is compliant with the  
IEEE 1394-1995 and IEEE 1394a-2000 specifications and supports asynchronous transfers.  
TSB43AA82 has a generic 16-/8-bit host bus interface. It supports parallel or multiplexed connections to the  
microcontroller (MCU) at rates up to 40 MHz.  
The TSB43AA82 offers large data transfers with three mutually independent FIFOs: 1) the asynchronous  
command FIFO with 1512 Bytes, 2) the DMA FIFO with 4728 bytes and 3) the Config ROM/LOG FIFO with 504  
bytes.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
12345

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