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TS83C51RB2ZZZ-MCBB PDF预览

TS83C51RB2ZZZ-MCBB

更新时间： 2024-02-11 09:04:31
品牌 Logo 应用领域
其他 - ETC 微控制器
页数 文件大小 规格书
74页 639K
描述
Microcontroller

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中文翻译

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TS83C51RB2ZZZ-MCBB 技术参数

生命周期：ObsoleteReach Compliance Code：unknown
风险等级：5.66Base Number Matches：1

TS83C51RB2ZZZ-MCBB 数据手册

 浏览型号TS83C51RB2ZZZ-MCBB的Datasheet PDF文件第2页浏览型号TS83C51RB2ZZZ-MCBB的Datasheet PDF文件第3页浏览型号TS83C51RB2ZZZ-MCBB的Datasheet PDF文件第4页浏览型号TS83C51RB2ZZZ-MCBB的Datasheet PDF文件第5页浏览型号TS83C51RB2ZZZ-MCBB的Datasheet PDF文件第6页浏览型号TS83C51RB2ZZZ-MCBB的Datasheet PDF文件第7页 
TS80C51RA2/RD2  
TS83C51RB2/RC2/RD2  
TS87C51RB2/RC2/RD2  
High Performance 8-bit Microcontrollers  
1. Description  
Atmel Wireless & Microcontrollers TS80C51Rx2 is high The fully static design of the TS80C51Rx2 allows to  
reduce system power consumption by bringing the clock  
frequency down to any value, even DC, without loss of  
data.  
performance CMOS ROM, OTP, EPROM and ROMless  
versions of the 80C51 CMOS single chip 8-bit  
microcontroller.  
The TS80C51Rx2 has 2 software-selectable modes of  
reduced activity for further reduction in power  
consumption. In the idle mode the CPU is frozen while  
the timers, the serial port and the interrupt system are still  
operating. In the power-down mode the RAM is saved  
and all other functions are inoperative.  
The TS80C51Rx2 retains all features of the 80C51 with  
extended ROM/EPROM capacity (16/32/64 Kbytes), 256  
bytes of internal RAM, a 7-source , 4-level interrupt  
system, an on-chip oscilator and three timer/counters.  
In addition, the TS80C51Rx2 has a Programmable  
Counter Array, an XRAM of 256 or 768 bytes, a  
Hardware Watchdog Timer, a more versatile serial  
channel that facilitates multiprocessor communication  
(EUART) and a X2 speed improvement mechanism.  
2. Features  
•
80C52 Compatible  
•
•
Hardware Watchdog Timer (One-time enabled with  
Reset-Out)  
•
•
•
•
8051 pin and instruction compatible  
Four 8-bit I/O ports  
2 extra 8-bit I/O ports available on RD2 with high  
pin count packages  
Three 16-bit timer/counters  
256 bytes scratchpad RAM  
•
•
Asynchronous port reset  
Interrupt Structure with  
•
High-Speed Architecture  
•
•
7 Interrupt sources,  
•
•
40 MHz @ 5V, 30MHz @ 3V  
4 level priority interrupt system  
X2 Speed Improvement capability (6 clocks/  
machine cycle)  
•
Full duplex Enhanced UART  
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to  
60 MHz @ 5V, 40 MHz @ 3V)  
•
•
Framing error detection  
Automatic address recognition  
•
•
Dual Data Pointer  
•
•
Low EMI (inhibit ALE)  
Power Control modes  
On-chip ROM/EPROM (16K-bytes, 32K-bytes, 64K-  
bytes)  
•
•
•
Idle mode  
•
•
On-chip eXpanded RAM (XRAM) (256 or 768 bytes)  
Power-down mode  
Power-off Flag  
Programmable Clock Out and Up/Down Timer/  
Counter 2  
•
•
•
Once mode (On-chip Emulation)  
•
Programmable Counter Array with  
Power supply: 4.5-5V, 2.7-5.5V  
Temperature ranges: Commercial (0 to 70oC) and  
Industrial (-40 to 85oC)  
•
•
•
•
High Speed Output,  
Compare / Capture,  
Pulse Width Modulator,  
Watchdog Timer Capabilities  
•
Packages: PDIL40, PLCC44, VQFP44 1.4, CQPJ44  
(window), CDIL40 (window), PLCC68, VQFP64  
1.4, JLCC68 (window)  
Rev. C - 06 March, 2001  
1
1234567...74

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