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TS80C32X2-MIBD PDF预览

TS80C32X2-MIBD

更新时间: 2024-01-28 00:33:49
品牌 Logo 应用领域
爱特美尔 - ATMEL 时钟微控制器光电二极管外围集成电路
页数 文件大小 规格书
56页 390K
描述
Microcontroller, 8-Bit, 8051 CPU, 40MHz, CMOS, PDIP40, PLASTIC, LCC-44

TS80C32X2-MIBD 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:LCC包装说明:QCCJ, LDCC44,.7SQ
针数:44Reach Compliance Code:compliant
ECCN代码:3A991.A.2HTS代码:8542.31.00.01
风险等级:5.69具有ADC:NO
地址总线宽度:16位大小:8
CPU系列:8051最大时钟频率:40 MHz
DAC 通道:NODMA 通道:NO
外部数据总线宽度:8JESD-30 代码:S-PQCC-J44
JESD-609代码:e0长度:16.5862 mm
湿度敏感等级:2I/O 线路数量:32
端子数量:44最高工作温度:85 °C
最低工作温度:-40 °CPWM 通道:NO
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC44,.7SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):225
电源:5 V认证状态:Not Qualified
RAM(字节):256ROM(单词):0
座面最大高度:4.57 mm速度:40 MHz
子类别:Microcontrollers最大压摆率:39 mA
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:16.5862 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLERBase Number Matches:1

TS80C32X2-MIBD 数据手册

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TS80C32X2  
TS87C52X2  
TS80C52X2  
8-bit Microcontroller 8 Kbytes ROM/OTP, ROMless  
1. Description  
TS80C52X2 is high performance CMOS ROM, OTP, The fully static design of the TS80C52X2 allows to  
reduce system power consumption by bringing the clock  
frequency down to any value, even DC, without loss of  
data.  
EPROM and ROMless versions of the 80C51 CMOS  
single chip 8-bit microcontroller.  
The TS80C52X2 retains all features of the 80C51 with  
extended ROM/EPROM capacity (8 Kbytes), 256 bytes  
of internal RAM, a 6-source , 4-level interrupt system,  
an on-chip oscilator and three timer/counters.  
The TS80C52X2 has 2 software-selectable modes of  
reduced activity for further reduction in power  
consumption. In the idle mode the CPU is frozen while  
the timers, the serial port and the interrupt system are still  
operating. In the power-down mode the RAM is saved  
and all other functions are inoperative.  
In addition, the TS80C52X2 has a dual data pointer, a  
more versatile serial channel that facilitates  
multiprocessor communication (EUART) and a X2 speed  
improvement mechanism.  
2. Features  
80C52 Compatible  
Interrupt Structure with  
8051 pin and instruction compatible  
Four 8-bit I/O ports  
6 Interrupt sources,  
4 level priority interrupt system  
Three 16-bit timer/counters  
256 bytes scratchpad RAM  
Full duplex Enhanced UART  
Framing error detection  
Automatic address recognition  
High-Speed Architecture  
40 MHz @ 5V, 30MHz @ 3V  
Low EMI (inhibit ALE)  
Power Control modes  
X2 Speed Improvement capability (6 clocks/  
machine cycle)  
Idle mode  
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to  
60 MHz @ 5V, 40 MHz @ 3V)  
Power-down mode  
Power-off Flag  
Dual Data Pointer  
Once mode (On-chip Emulation)  
Power supply: 4.5-5.5V, 2.7-5.5V  
On-chip ROM/EPROM (8Kbytes)  
Programmable Clock Out and Up/Down Timer/  
Temperature ranges: Commercial (0 to 70oC) and  
Counter 2  
Industrial (-40 to 85oC)  
Asynchronous port reset  
Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP F1  
(13.9 footprint), CQPJ44 (window), CDIL40  
(window)  
Rev.D - 16 November, 2000  
1

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