TPS62200, TPS62201
TPS62202, TPS62203, TPS62207
TPS62204, TPS62205, TPS62208
www.ti.com
SLVS417E–MARCH 2002–REVISED MAY 2006
FUNCTIONAL BLOCK DIAGRAM
V
I
Current Limit Comparator
+
_
Undervoltage
Lockout
Bias Supply
REF
+
_
Skip Comparator
REF
Soft Start
V
V
1 MHz
Oscillator
(COMP)
I
P-Channel
Power MOSFET
Comparator
S
R
Driver
Shoot-Through
Logic
SW
+
_
Control
Logic
Sawtooth
Generator
N-Channel
Power MOSFET
Comparator High
Comparator Low
Comparator Low 2
Load Comparator
+
_
Comparator High
+
_
R1
Compensation
Gm
R2
Comparator Low
Comparator Low 2
See Note
+
_
V
REF
= 0.5 V
EN
FB
GND
For the adjustable version (TPS62200) the internal feedback divider is disabled and the FB pin is directly connected
to the internal GM amplifier
DETAILED DESCRIPTION
OPERATION
The TPS6220x is a synchronous step-down converter operating with typically 1-MHz fixed frequency pulse width
modulation (PWM) at moderate to heavy load currents and in power save mode operating with pulse frequency
modulation (PFM) at light load currents.
During PWM operation the converter uses a unique fast response, voltage mode, controller scheme with input
voltage feed forward. This achieves good line and load regulation and allows the use of small ceramic input and
output capacitors. At the beginning of each clock cycle initiated by the clock signal (S), the P-channel MOSFET
switch is turned on, and the inductor current ramps up until the comparator trips and the control logic turns off
the switch. The current limit comparator also turns off the switch in case the current limit of the P-channel switch
is exceeded. Then the N-channel rectifier switch is turned on and the inductor current ramps down. The next
cycle is initiated by the clock signal again turning off the N-channel rectifier and turning on the P-channel switch.
3
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