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TN0520 PDF预览

TN0520

更新时间： 2024-02-10 11:32:23
品牌 Logo 应用领域
超科 - SUPERTEX /
页数 文件大小 规格书
4页 60K
描述
N-Channel Enhancement-Mode Vertical DMOS FETs

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中文翻译

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TN0520 技术参数

是否Rohs认证：不符合生命周期：Obsolete
包装说明：UNCASED CHIP, S-XUUC-N3Reach Compliance Code：unknown
ECCN代码：EAR99风险等级：5.92
Is Samacsys：N其他特性：HIGH INPUT IMPEDANCE
配置：SINGLE WITH BUILT-IN DIODE最小漏源击穿电压：200 V
最大漏源导通电阻：10 ΩFET 技术：METAL-OXIDE SEMICONDUCTOR
最大反馈电容 (Crss)：8 pFJESD-30 代码：S-XUUC-N3
JESD-609代码：e0元件数量：1
端子数量：3工作模式：ENHANCEMENT MODE
最高工作温度：150 °C封装主体材料：UNSPECIFIED
封装形状：SQUARE封装形式：UNCASED CHIP
峰值回流温度（摄氏度）：NOT SPECIFIED极性/信道类型：N-CHANNEL
认证状态：Not Qualified子类别：FET General Purpose Power
表面贴装：YES端子面层：TIN LEAD
端子形式：NO LEAD端子位置：UPPER
处于峰值回流温度下的最长时间：NOT SPECIFIED晶体管应用：SWITCHING
晶体管元件材料：SILICONBase Number Matches：1

TN0520 数据手册

 浏览型号TN0520的Datasheet PDF文件第2页浏览型号TN0520的Datasheet PDF文件第3页浏览型号TN0520的Datasheet PDF文件第4页 
TN0520  
TN0524  
Low Threshold  
N-Channel Enhancement-Mode  
Vertical DMOS FETs  
Ordering Information  
Order Number / Package  
TO-92  
BVDSS  
/
RDS(ON)  
ID(ON)  
VGS(th)  
(max)  
BVDGS  
200V  
240V  
(max)  
(min)  
300mA  
300mA  
TO-39  
TN0520N2  
—
Die†  
10Ω  
10Ω  
1.5V  
1.5V  
TN0520N3  
TN0520ND  
TN0524ND  
TN0524N3  
† MIL visual screening available  
7
High Reliability Devices  
Low Threshold DMOS Technology  
See pages 5-4 and 5-5 for MILITARY STANDARD Process  
Flows and Ordering Information.  
These low threshold enhancement-mode (normally-off) transis-  
tors utilize a vertical DMOS structure and Supertex's well-proven  
silicon-gate manufacturing process. This combination produces  
devices with the power handling capabilities of bipolar transistors  
and with the high input impedance and positive temperature  
coefficient inherent in MOS devices. Characteristic of all MOS  
structures, these devices are free from thermal runaway and  
thermally-induced secondary breakdown.  
Features  
■
■
■
■
■
■
■
■
Low threshold —1.5V max.  
High input impedance  
Low input capacitance — 45pF typical  
Fast switching speeds  
Supertex’s vertical DMOS FETs are ideally suited to a wide range  
of switching and amplifying applications where very low threshold  
voltage, highbreakdownvoltage, highinputimpedance, lowinput  
capacitance, and fast switching speeds are desired.  
Low on resistance  
Free from secondary breakdown  
Low input and output leakage  
Complementary N- and P-channel devices  
Package Options  
Applications  
■
■
■
■
■
■
■
Logic level interfaces – ideal for TTL and CMOS  
Solid state relays  
Battery operated systems  
Photo voltaic drives  
Analog switches  
General purpose line drivers  
Telecom switches  
S G D  
G
D
S
Absolute Maximum Ratings  
Drain-to-Source Voltage  
Drain-to-Gate Voltage  
Gate-to-Source Voltage  
TO-92  
TO-39  
Case: DRAIN  
BVDSS  
BVDGS  
± 20V  
Operating and Storage Temperature  
Soldering Temperature*  
-55°C to +150°C  
300°C  
Note: See Package Outline section for dimensions.  
* Distance of 1.6 mm from case for 10 seconds.  
7-39  
1234

中文翻译

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