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TMS320DM6433ZWT6 PDF预览

TMS320DM6433ZWT6

更新时间： 2024-01-15 01:14:54
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
271页 2268K
描述
Digital Media Processor

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TMS320DM6433ZWT6 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：BGA
包装说明：LFBGA, BGA361,19X19,32针数：361
Reach Compliance Code：compliantECCN代码：3A991.A.2
HTS代码：8542.31.00.01风险等级：2.22
其他特性：ALSO REQUIRES 3.3V SUPPLY地址总线宽度：32
桶式移位器：NO位大小：32
边界扫描：YES最大时钟频率：27 MHz
外部数据总线宽度：32格式：FIXED POINT
集成缓存：YES内部总线架构：MULTIPLE
JESD-30 代码：S-PBGA-B361JESD-609代码：e1
长度：16 mm低功率模式：YES
湿度敏感等级：3DMA 通道数量：72
端子数量：361计时器数量：5
片上数据RAM宽度：8片上程序ROM宽度：8
最高工作温度：90 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：LFBGA
封装等效代码：BGA361,19X19,32封装形状：SQUARE
封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
电源：1.2,1.8,3.3 V认证状态：Not Qualified
RAM（字数）：20480ROM可编程性：MROM
座面最大高度：1.4 mm子类别：Digital Signal Processors
最大供电电压：1.26 V最小供电电压：1.14 V
标称供电电压：1.2 V表面贴装：YES
技术：CMOS温度等级：OTHER
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：16 mm
uPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches：1

TMS320DM6433ZWT6 数据手册

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TMS320DM6433  
Digital Media Processor  
www.ti.com  
SPRS343C–NOVEMBER 2006–REVISED JUNE 2008  
1 TMS320DM6433 Digital Media Processor  
1.1 Features  
–
–
–
256K-Bit (32K-Byte) L1P Program  
RAM/Cache [Flexible Allocation]  
640K-Bit (80K-Byte) L1D Data RAM/Cache  
[Flexible Allocation]  
1M-Bit (128K-Byte) L2 Unified Mapped  
RAM/Cache [Flexible Allocation]  
•
High-Performance Digital Media Processor  
(DM6433)  
–
2.5-, 2-, 1.67-, 1.51-, 1.43-ns ns Instruction  
Cycle Time  
–
400-, 500, -600-, 660-, 700-MHz C64x+™  
Clock Rate  
•
•
Supports Little Endian Mode Only  
Video Processing Subsystem (VPSS)  
–
–
–
–
Eight 32-Bit C64x+ Instructions/Cycle  
3200, 4000, 4800, 5280, 5600 MIPS  
Fully Software-Compatible With C64x  
Commercial and Automotive (Q or S suffix)  
Grades  
–
Front End Provides (Resizer Only):  
•
•
Resize Images From 1/4x to 4x  
Separate Horizontal and Vertical Control  
–
Low-Power Device (L suffix)  
–
Back End Provides:  
•
VelociTI.2™ Extensions to VelociTI™  
Advanced Very-Long-Instruction-Word (VLIW)  
TMS320C64x+™ DSP Core  
•
•
Hardware On-Screen Display (OSD)  
Four 54-MHz DACs for a Combination of  
–
–
Composite NTSC/PAL Video  
Luma/Chroma Separate Video  
(S-video)  
–
Eight Highly Independent Functional Units  
With VelociTI.2 Extensions:  
•
Six ALUs (32-/40-Bit), Each Supports  
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit  
Arithmetic per Clock Cycle  
–
Component (YPbPr or RGB) Video  
(Progressive)  
•
Digital Output  
•
Two Multipliers Support Four 16 x 16-Bit  
Multiplies (32-Bit Results) per Clock  
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit  
Results) per Clock Cycle  
–
–
–
8-/16-bit YUV or up to 24-Bit RGB  
HD Resolution  
Up to 2 Video Windows  
•
External Memory Interfaces (EMIFs)  
–
Load-Store Architecture With Non-Aligned  
Support  
64 32-Bit General-Purpose Registers  
Instruction Packing Reduces Code Size  
All Instructions Conditional  
–
32-Bit DDR2 SDRAM Memory Controller  
With 256M-Byte Address Space (1.8-V I/O)  
–
–
–
–
•
Supports up to 333-MHz (data rate) bus  
and interfaces to DDR2-400 SDRAM  
–
Asynchronous 8-Bit Wide EMIF (EMIFA)  
With up to 64M-Byte Address Reach  
Additional C64x+™ Enhancements  
•
•
Protected Mode Operation  
Exceptions Support for Error Detection  
and Program Redirection  
•
Flash Memory Interfaces  
–
–
NOR (8-Bit-Wide Data)  
NAND (8-Bit-Wide Data)  
•
Hardware Support for Modulo Loop  
Auto-Focus Module Operation  
•
•
Enhanced Direct-Memory-Access (EDMA)  
Controller (64 Independent Channels)  
•
C64x+ Instruction Set Features  
Two 64-Bit General-Purpose Timers (Each  
Configurable as Two 32-Bit Timers)  
–
–
–
–
–
–
Byte-Addressable (8-/16-/32-/64-Bit Data)  
8-Bit Overflow Protection  
Bit-Field Extract, Set, Clear  
Normalization, Saturation, Bit-Counting  
VelociTI.2 Increased Orthogonality  
C64x+ Extensions  
•
•
•
One 64-Bit Watch Dog Timer  
One UART With RTS and CTS Flow Control  
Master/Slave Inter-Integrated Circuit (I2C  
Bus™)  
•
•
Compact 16-bit Instructions  
Additional Instructions to Support  
Complex Multiplies  
•
One Multichannel Buffered Serial Port  
(McBSP0)  
–
–
I2S and TDM  
AC97 Audio Codec Interface  
•
C64x+ L1/L2 Memory Architecture  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this document.  
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2006–2008, Texas Instruments Incorporated  
 
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