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TMS28F200AFT60BDCDL PDF预览

TMS28F200AFT60BDCDL

更新时间: 2024-09-29 00:34:31
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德州仪器 - TI /
页数 文件大小 规格书
79页 1109K
描述
262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

TMS28F200AFT60BDCDL 数据手册

 浏览型号TMS28F200AFT60BDCDL的Datasheet PDF文件第2页浏览型号TMS28F200AFT60BDCDL的Datasheet PDF文件第3页浏览型号TMS28F200AFT60BDCDL的Datasheet PDF文件第4页浏览型号TMS28F200AFT60BDCDL的Datasheet PDF文件第5页浏览型号TMS28F200AFT60BDCDL的Datasheet PDF文件第6页浏览型号TMS28F200AFT60BDCDL的Datasheet PDF文件第7页 
TMS28F002Axy, TMS28F200Axy  
262144 BY 8-BIT/131072 BY 16-BIT  
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES  
SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997  
DBJ PACKAGE  
(TOP VIEW)  
Organization . . . 262144 by 8 bits  
131072 by 16 bits  
Array-Blocking Architecture  
V
1
2
3
4
5
6
7
8
9
44 RP  
PP  
– One 16K-Byte Protected Boot Block  
– Two 8K-Byte Parameter Blocks  
– One 96K-Byte Main Block  
– One 128K-Byte Main Block  
– Top or Bottom Boot Locations  
DU/WP  
NC  
A7  
43  
W
42  
A8  
41 A9  
A6  
A5  
A4  
A3  
40 A10  
39 A11  
38 A12  
37 A13  
36 A14  
’28F200Axy Offers a User-Defined 8-Bit  
(Byte) or 16-Bit (Word) Organization  
A2  
35  
34  
33  
32  
A1 10  
A0 11  
A15  
A16  
BYTE  
’28F002Axy Offers Only the 8-Bit (Byte)  
Organization  
E
12  
13  
14  
Maximum Access/Minimum Cycle Time  
– Commercial and Extended  
V
V
SS  
G
SS  
31 DQ15/A  
30 DQ7  
29 DQ14  
28 DQ6  
–1  
5-V V  
10% or 3.3-V V  
0.3 V  
3.3 V  
DQ0 15  
DQ8 16  
DQ1 17  
DQ9 18  
DQ2 19  
DQ10 20  
DQ3 21  
DQ11 22  
CC  
CC  
5 V  
’28F002Axy/200Axy60 60 ns 110 ns  
’28F002Axy/200Axy70 70 ns 130 ns  
’28F002Axy/200Axy80 80 ns 150 ns  
27  
DQ13  
26 DQ5  
25 DQ12  
24 DQ4  
– Automotive  
5-V V  
10%  
23  
V
CC  
CC  
’28F200Axy70  
’28F200Axy80  
’28F200Axy90  
70 ns  
80 ns  
90 ns  
PIN NOMENCLATURE  
A0A16  
A17  
Address Inputs  
(x = S, E, F, Z, or M Depending on V /V  
Address Input (40-Pin Package Only)  
Byte-Enable  
CC PP  
BYTE  
Voltage Configuration)  
DQ0DQ14 Data In/Out  
(y = T for Top or B for Bottom Boot-Block  
Configuration)  
DQ15/A  
Data In/Out (Word-Wide Mode),  
–1  
Low-Order Address (Byte-Wide Mode)  
Chip-Enable  
100000- and 10000-Program/Erase-Cycle  
Versions  
E
G
Output-Enable  
Three Temperature Ranges  
NC  
RP  
No Internal Connection  
Reset/Deep Power-Down  
Power Supply  
– Commercial . . . 0°C to 70°C  
– Extended . . . – 40°C to 85°C  
– Automotive . . . – 40°C to 125°C  
V
CC  
V
PP  
Power Supply for Program/Erase  
Ground  
V
SS  
Industry Standard Packages Offered in  
– 40-pin Thin Small-Outline Package  
(TSOP)  
W
Write-Enable  
DU/WP  
Do Not Use for AMy or AZy/Write-Protect  
– 44-pin Plastic Small-Outline Package  
(PSOP)  
– 48-pin TSOP  
Fully Automated On-Chip Erase and  
Word/Byte Program Operations  
Write-Protection for Boot Block  
Low Power Dissipation (V  
= 5.5 V)  
CC  
Industry Standard Command-State Machine  
(CSM)  
– Erase Suspend/Resume  
– Algorithm-Selection Identifier  
– Active Read . . . 330 mW (Byte-Read)  
– Active Write . . . 248 mW (Byte-Write)  
– Active Read . . . 330 mW (Word-Read)  
– Active Write . . . 248 mW (Word-Write)  
– Block-Erase . . . 165 mW  
Five Different Combinations of Supply  
Voltages Offered  
– Standby . . . 0.72 mW (CMOS-Input  
Levels)  
All Inputs/Outputs TTL-Compatible  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443  

TMS28F200AFT60BDCDL 替代型号

型号 品牌 替代类型 描述 数据表
TE28F200B5T80 INTEL

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E28F200B5T60 INTEL

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SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT

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