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TLV5535IPWRG4Q1 PDF预览

TLV5535IPWRG4Q1

更新时间： 2024-01-15 01:09:30
品牌 Logo 应用领域
德州仪器 - TI 转换器
页数 文件大小 规格书
36页 667K
描述
8-BIT, 35 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER

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TLV5535IPWRG4Q1 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SSOP
包装说明：TSSOP, TSSOP28,.25针数：28
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：5.8最大模拟输入电压：3.5 V
最小模拟输入电压：0.8 V最长转换时间：0.0285 µs
转换器类型：ADC, PROPRIETARY METHODJESD-30 代码：R-PDSO-G28
JESD-609代码：e4长度：9.7 mm
最大线性误差 (EL)：0.9375%湿度敏感等级：1
模拟输入通道数量：1位数：8
功能数量：1端子数量：28
最高工作温度：85 °C最低工作温度：-40 °C
输出位码：BINARY输出格式：PARALLEL, 8 BITS
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP28,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
采样速率：35 MHz采样并保持/跟踪并保持：SAMPLE
筛选级别：AEC-Q100座面最大高度：1.2 mm
子类别：Analog to Digital Converters最大压摆率：34 mA
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.4 mm
Base Number Matches：1

TLV5535IPWRG4Q1 数据手册

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ꢀ ꢁꢂ ꢃ ꢃꢄ ꢃ ꢅꢆꢇ  
ꢈꢅ ꢉꢊ ꢀꢋ ꢄ ꢃ ꢌ ꢍꢎꢍꢋ ꢁꢏ ꢐꢅꢎ ꢏꢐ ꢑ ꢒ ꢓꢔ ꢓꢁ ꢏꢕ ꢅꢀꢏ ꢅꢖꢊꢕ ꢊ ꢀꢓꢁ ꢗꢏ ꢔꢂꢑ ꢒꢀ ꢑꢒ  
SGLS230A − JANUARY 2004 − REVISED JUNE 2008  
electrical characteristics over recommended operating conditions, f  
voltage references (unless otherwise noted) (continued)  
= 35 MSPS, external  
CLK  
logic outputs  
PARAMETER  
TEST CONDITIONS  
= DRV = 3 V at I  
MIN  
TYP  
MAX  
UNIT  
AV  
DD  
= DV  
DD  
= 50 µA,  
DD OH  
V
V
High-level output voltage  
2.8  
V
OH  
Digital output forced high  
AV = DV = DRV  
Digital output forced low  
= 3.6 V at I  
= 50 µA,  
DD DD DD  
OL  
Low-level output voltage  
Output capacitance  
0.1  
V
OL  
C
5
pF  
µA  
O
High-impedance state output current to  
high level  
I
10  
10  
OZH  
AV  
DD  
= DV  
DD  
= DRV = 3.6 V  
DD  
High-impedance state output current to  
low level  
I
µA  
OZL  
dc accuracy  
PARAMETER  
TEST CONDITIONS  
MIN  
−1.5  
−2.4  
−1  
TYP  
0.7  
0.7  
0.6  
MAX  
1.5  
2.4  
1.3  
5
UNIT  
LSB  
LSB  
LSB  
%FS  
%FS  
T
= 25°C  
A
Integral nonlinearity (INL), best-fit  
Internal references (see Note 1)  
Internal references (see Note 2),  
T
= −40°C to 85°C  
T = −40°C to 85°C  
A
A
Differential nonlinearity (DNL)  
Zero error  
AV  
DD  
= DV  
DD  
= 3.3 V, DRV = 3 V,  
DD  
Internal references (see Note 3)  
Full-scale error  
5
NOTES: 1. Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The point used as zero  
occurs 1/2 LSB before the first code transition. The full-scale point is defined as a level 1/2 LSB beyond the last code transition. The  
deviation is measured from the center of each particular code to the true straight line between these two endpoints.  
2. An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore this measure  
indicates how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under  
n
test [i.e., (last transition level − first transition level) ÷ (2 − 2)]. Using this definition for DNL separates the effects of gain and offset  
error. A minimum DNL better than −1 LSB ensures no missing codes.  
3. Zero error is defined as the difference in analog input voltage − between the ideal voltage and the actual voltage − that switches  
the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the  
bottom reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by  
the number of ADC output levels (256).  
Full-scale error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that switches  
the ADC output from code 254 to code 255. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5  
LSB from the top reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references  
divided by the number of ADC output levels (256).  
analog input  
PARAMETER  
Input capacitance  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
C
4
pF  
I
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1...3456789...36

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