TMS320DM355
Digital Media System-on-Chip (DMSoC)
www.ti.com
SPRS463F–SEPTEMBER 2007–REVISED JANUARY 2009
1 TMS320DM355 Digital Media System-on-Chip (DMSoC)
1.1 Features
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8-/16-bit YCC and Up to 18-Bit RGB666
Digital Output
BT.601/BT.656 Digital YCbCr 4:2:2
(8-/16-Bit) Interface
Supports digital HDTV (720p/1080i)
output for connection to external
encoder
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High-Performance Digital Media
System-on-Chip
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135-, 216-, and 270-MHz ARM926EJ-S Clock
Rate
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Fully Software-Compatible With ARM9™
Extended temperature support for 135- and
216-MHz devices
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External Memory Interfaces (EMIFs)
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ARM926EJ-S Core
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DDR2 and mDDR SDRAM 16-bit wide EMIF
With 256 MByte Address Space (1.8-V I/O)
Asynchronous16-/8-bit Wide EMIF (AEMIF)
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Support for 32-Bit and 16-Bit (Thumb Mode)
Instruction Sets
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DSP Instruction Extensions and Single
Cycle MAC
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Flash Memory Interfaces
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NAND (8-/16-bit Wide Data)
OneNAND(16-bit Wide Data)
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ARM® Jazelle® Technology
EmbeddedICE-RT™ Logic for Real-Time
Debug
Flash Card Interfaces
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Two Multimedia Card (MMC) / Secure
Digital (SD/SDIO)
SmartMedia
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ARM9 Memory Architecture
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16K-Byte Instruction Cache
8K-Byte Data Cache
32K-Byte RAM
8K-Byte ROM
Little Endian
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Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
USB Port with Integrated 2.0 High-Speed PHY
that Supports
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Three 64-Bit General-Purpose Timers (each
configurable as two 32-bit timers)
One 64-Bit Watch Dog Timer
Three UARTs (One fast UART with RTS and
CTS Flow Control)
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MPEG4/JPEG Coprocessor
Fixed Function Coprocessor Supports:
USB 2.0 Full and High-Speed Device
USB 2.0 Low, Full, and High-Speed Host
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MPEG4 SP Codec at HD (720p), D1,
VGA, SIF
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JPEG Codec up to 50M Pixels per
Second
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Video Processing Subsystem
– Front End Provides:
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Three Serial Port Interfaces (SPI) each with
two Chip-Selects
One Master/Slave Inter-Integrated Circuit (I2C)
Bus®
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Hardware IPIPE for Real-Time Image
Processing
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Up to 14-bit CCD/CMOS Digital Interface
16-/8-bit Generic YcBcR-4:2 Interface
(BT.601)
Two Audio Serial Port (ASP)
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I2S and TDM I2S
AC97 Audio Codec Interface
S/PDIF via Software
Standard Voice Codec Interface (AIC12)
SPI Protocol (Master Mode Only)
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10-/8-bit CCIR6565/BT655 Interface
Up to 75-MHz Pixel Clock
Histogram Module
Resize Engine
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Resize Images From 1/16x to 8x
Separate Horizontal/Vertical Control
Two Simultaneous Output Paths
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Four Pulse Width Modulator (PWM) Outputs
Four RTO (Real Time Out) Outputs
Up to 104 General-Purpose I/O (GPIO) Pins
(Multiplexed with Other Device Functions)
On-Chip ARM ROM Bootloader (RBL) to Boot
From NAND Flash, MMC/SD, or UART
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Back End Provides:
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Hardware On-Screen Display (OSD)
Composite NTSC/PAL video encoder
output
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